242 lines
8.5 KiB
Plaintext
242 lines
8.5 KiB
Plaintext
STMicroelectronics stih4xx platforms
|
|
|
|
- sti-vtg: video timing generator
|
|
Required properties:
|
|
- compatible: "st,vtg"
|
|
- reg: Physical base address of the IP registers and length of memory mapped region.
|
|
Optional properties:
|
|
- interrupts : VTG interrupt number to the CPU.
|
|
- st,slave: phandle on a slave vtg
|
|
|
|
- sti-vtac: video timing advanced inter dye communication Rx and TX
|
|
Required properties:
|
|
- compatible: "st,vtac-main" or "st,vtac-aux"
|
|
- reg: Physical base address of the IP registers and length of memory mapped region.
|
|
- clocks: from common clock binding: handle hardware IP needed clocks, the
|
|
number of clocks may depend of the SoC type.
|
|
See ../clocks/clock-bindings.txt for details.
|
|
- clock-names: names of the clocks listed in clocks property in the same
|
|
order.
|
|
|
|
- sti-display-subsystem: Master device for DRM sub-components
|
|
This device must be the parent of all the sub-components and is responsible
|
|
of bind them.
|
|
Required properties:
|
|
- compatible: "st,sti-display-subsystem"
|
|
- ranges: to allow probing of subdevices
|
|
|
|
- sti-compositor: frame compositor engine
|
|
must be a child of sti-display-subsystem
|
|
Required properties:
|
|
- compatible: "st,stih<chip>-compositor"
|
|
- reg: Physical base address of the IP registers and length of memory mapped region.
|
|
- clocks: from common clock binding: handle hardware IP needed clocks, the
|
|
number of clocks may depend of the SoC type.
|
|
See ../clocks/clock-bindings.txt for details.
|
|
- clock-names: names of the clocks listed in clocks property in the same
|
|
order.
|
|
- resets: resets to be used by the device
|
|
See ../reset/reset.txt for details.
|
|
- reset-names: names of the resets listed in resets property in the same
|
|
order.
|
|
- st,vtg: phandle(s) on vtg device (main and aux) nodes.
|
|
|
|
- sti-tvout: video out hardware block
|
|
must be a child of sti-display-subsystem
|
|
Required properties:
|
|
- compatible: "st,stih<chip>-tvout"
|
|
- reg: Physical base address of the IP registers and length of memory mapped region.
|
|
- reg-names: names of the mapped memory regions listed in regs property in
|
|
the same order.
|
|
- resets: resets to be used by the device
|
|
See ../reset/reset.txt for details.
|
|
- reset-names: names of the resets listed in resets property in the same
|
|
order.
|
|
|
|
- sti-hdmi: hdmi output block
|
|
must be a child of sti-display-subsystem
|
|
Required properties:
|
|
- compatible: "st,stih<chip>-hdmi";
|
|
- reg: Physical base address of the IP registers and length of memory mapped region.
|
|
- reg-names: names of the mapped memory regions listed in regs property in
|
|
the same order.
|
|
- interrupts : HDMI interrupt number to the CPU.
|
|
- interrupt-names: names of the interrupts listed in interrupts property in
|
|
the same order
|
|
- clocks: from common clock binding: handle hardware IP needed clocks, the
|
|
number of clocks may depend of the SoC type.
|
|
- clock-names: names of the clocks listed in clocks property in the same
|
|
order.
|
|
- ddc: phandle of an I2C controller used for DDC EDID probing
|
|
|
|
sti-hda:
|
|
Required properties:
|
|
must be a child of sti-display-subsystem
|
|
- compatible: "st,stih<chip>-hda"
|
|
- reg: Physical base address of the IP registers and length of memory mapped region.
|
|
- reg-names: names of the mapped memory regions listed in regs property in
|
|
the same order.
|
|
- clocks: from common clock binding: handle hardware IP needed clocks, the
|
|
number of clocks may depend of the SoC type.
|
|
See ../clocks/clock-bindings.txt for details.
|
|
- clock-names: names of the clocks listed in clocks property in the same
|
|
order.
|
|
|
|
sti-dvo:
|
|
Required properties:
|
|
must be a child of sti-display-subsystem
|
|
- compatible: "st,stih<chip>-dvo"
|
|
- reg: Physical base address of the IP registers and length of memory mapped region.
|
|
- reg-names: names of the mapped memory regions listed in regs property in
|
|
the same order.
|
|
- clocks: from common clock binding: handle hardware IP needed clocks, the
|
|
number of clocks may depend of the SoC type.
|
|
See ../clocks/clock-bindings.txt for details.
|
|
- clock-names: names of the clocks listed in clocks property in the same
|
|
order.
|
|
- pinctrl-0: pin control handle
|
|
- pinctrl-names: names of the pin control states to use
|
|
- sti,panel: phandle of the panel connected to the DVO output
|
|
|
|
sti-hqvdp:
|
|
must be a child of sti-display-subsystem
|
|
Required properties:
|
|
- compatible: "st,stih<chip>-hqvdp"
|
|
- reg: Physical base address of the IP registers and length of memory mapped region.
|
|
- clocks: from common clock binding: handle hardware IP needed clocks, the
|
|
number of clocks may depend of the SoC type.
|
|
See ../clocks/clock-bindings.txt for details.
|
|
- clock-names: names of the clocks listed in clocks property in the same
|
|
order.
|
|
- resets: resets to be used by the device
|
|
See ../reset/reset.txt for details.
|
|
- reset-names: names of the resets listed in resets property in the same
|
|
order.
|
|
- st,vtg: phandle on vtg main device node.
|
|
|
|
Example:
|
|
|
|
/ {
|
|
...
|
|
|
|
vtg_main_slave: sti-vtg-main-slave@fe85a800 {
|
|
compatible = "st,vtg";
|
|
reg = <0xfe85A800 0x300>;
|
|
interrupts = <GIC_SPI 175 IRQ_TYPE_NONE>;
|
|
};
|
|
|
|
vtg_main: sti-vtg-main-master@fd348000 {
|
|
compatible = "st,vtg";
|
|
reg = <0xfd348000 0x400>;
|
|
st,slave = <&vtg_main_slave>;
|
|
};
|
|
|
|
vtg_aux_slave: sti-vtg-aux-slave@fd348400 {
|
|
compatible = "st,vtg";
|
|
reg = <0xfe858200 0x300>;
|
|
interrupts = <GIC_SPI 176 IRQ_TYPE_NONE>;
|
|
};
|
|
|
|
vtg_aux: sti-vtg-aux-master@fd348400 {
|
|
compatible = "st,vtg";
|
|
reg = <0xfd348400 0x400>;
|
|
st,slave = <&vtg_aux_slave>;
|
|
};
|
|
|
|
|
|
sti-vtac-rx-main@fee82800 {
|
|
compatible = "st,vtac-main";
|
|
reg = <0xfee82800 0x200>;
|
|
clock-names = "vtac";
|
|
clocks = <&clk_m_a2_div0 CLK_M_VTAC_MAIN_PHY>;
|
|
};
|
|
|
|
sti-vtac-rx-aux@fee82a00 {
|
|
compatible = "st,vtac-aux";
|
|
reg = <0xfee82a00 0x200>;
|
|
clock-names = "vtac";
|
|
clocks = <&clk_m_a2_div0 CLK_M_VTAC_AUX_PHY>;
|
|
};
|
|
|
|
sti-vtac-tx-main@fd349000 {
|
|
compatible = "st,vtac-main";
|
|
reg = <0xfd349000 0x200>, <0xfd320000 0x10000>;
|
|
clock-names = "vtac";
|
|
clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
|
|
};
|
|
|
|
sti-vtac-tx-aux@fd349200 {
|
|
compatible = "st,vtac-aux";
|
|
reg = <0xfd349200 0x200>, <0xfd320000 0x10000>;
|
|
clock-names = "vtac";
|
|
clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
|
|
};
|
|
|
|
sti-display-subsystem {
|
|
compatible = "st,sti-display-subsystem";
|
|
ranges;
|
|
|
|
sti-compositor@fd340000 {
|
|
compatible = "st,stih416-compositor";
|
|
reg = <0xfd340000 0x1000>;
|
|
clock-names = "compo_main", "compo_aux",
|
|
"pix_main", "pix_aux";
|
|
clocks = <&clk_m_a2_div1 CLK_M_COMPO_MAIN>, <&clk_m_a2_div1 CLK_M_COMPO_AUX>,
|
|
<&clockgen_c_vcc CLK_S_PIX_MAIN>, <&clockgen_c_vcc CLK_S_PIX_AUX>;
|
|
reset-names = "compo-main", "compo-aux";
|
|
resets = <&softreset STIH416_COMPO_M_SOFTRESET>, <&softreset STIH416_COMPO_A_SOFTRESET>;
|
|
st,vtg = <&vtg_main>, <&vtg_aux>;
|
|
};
|
|
|
|
sti-tvout@fe000000 {
|
|
compatible = "st,stih416-tvout";
|
|
reg = <0xfe000000 0x1000>, <0xfe85a000 0x400>, <0xfe830000 0x10000>;
|
|
reg-names = "tvout-reg", "hda-reg", "syscfg";
|
|
reset-names = "tvout";
|
|
resets = <&softreset STIH416_HDTVOUT_SOFTRESET>;
|
|
};
|
|
|
|
sti-hdmi@fe85c000 {
|
|
compatible = "st,stih416-hdmi";
|
|
reg = <0xfe85c000 0x1000>, <0xfe830000 0x10000>;
|
|
reg-names = "hdmi-reg", "syscfg";
|
|
interrupts = <GIC_SPI 173 IRQ_TYPE_NONE>;
|
|
interrupt-names = "irq";
|
|
clock-names = "pix", "tmds", "phy", "audio";
|
|
clocks = <&clockgen_c_vcc CLK_S_PIX_HDMI>, <&clockgen_c_vcc CLK_S_TMDS_HDMI>, <&clockgen_c_vcc CLK_S_HDMI_REJECT_PLL>, <&clockgen_b1 CLK_S_PCM_0>;
|
|
};
|
|
|
|
sti-hda@fe85a000 {
|
|
compatible = "st,stih416-hda";
|
|
reg = <0xfe85a000 0x400>, <0xfe83085c 0x4>;
|
|
reg-names = "hda-reg", "video-dacs-ctrl";
|
|
clock-names = "pix", "hddac";
|
|
clocks = <&clockgen_c_vcc CLK_S_PIX_HD>, <&clockgen_c_vcc CLK_S_HDDAC>;
|
|
};
|
|
|
|
sti-dvo@8d00400 {
|
|
compatible = "st,stih407-dvo";
|
|
reg = <0x8d00400 0x200>;
|
|
reg-names = "dvo-reg";
|
|
clock-names = "dvo_pix", "dvo",
|
|
"main_parent", "aux_parent";
|
|
clocks = <&clk_s_d2_flexgen CLK_PIX_DVO>, <&clk_s_d2_flexgen CLK_DVO>,
|
|
<&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_dvo>;
|
|
sti,panel = <&panel_dvo>;
|
|
};
|
|
|
|
sti-hqvdp@9c000000 {
|
|
compatible = "st,stih407-hqvdp";
|
|
reg = <0x9C00000 0x100000>;
|
|
clock-names = "hqvdp", "pix_main";
|
|
clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
|
|
reset-names = "hqvdp";
|
|
resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
|
|
st,vtg = <&vtg_main>;
|
|
};
|
|
};
|
|
...
|
|
};
|