492 lines
16 KiB
C
492 lines
16 KiB
C
/*
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* arch/arm/include/asm/io.h
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*
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* Copyright (C) 1996-2000 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Modifications:
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* 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
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* constant addresses and variable addresses.
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* 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
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* specific IO header files.
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* 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
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* 04-Apr-1999 PJB Added check_signature.
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* 12-Dec-1999 RMK More cleanups
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* 18-Jun-2000 RMK Removed virt_to_* and friends definitions
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* 05-Oct-2004 BJD Moved memory string functions to use void __iomem
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*/
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#ifndef __ASM_ARM_IO_H
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#define __ASM_ARM_IO_H
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#ifdef __KERNEL__
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#include <linux/string.h>
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#include <linux/types.h>
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#include <asm/byteorder.h>
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#include <asm/memory.h>
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#include <asm-generic/pci_iomap.h>
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#include <xen/xen.h>
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/*
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* ISA I/O bus memory addresses are 1:1 with the physical address.
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*/
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#define isa_virt_to_bus virt_to_phys
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#define isa_page_to_bus page_to_phys
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#define isa_bus_to_virt phys_to_virt
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/*
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* Atomic MMIO-wide IO modify
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*/
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extern void atomic_io_modify(void __iomem *reg, u32 mask, u32 set);
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extern void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set);
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/*
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* Generic IO read/write. These perform native-endian accesses. Note
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* that some architectures will want to re-define __raw_{read,write}w.
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*/
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void __raw_writesb(volatile void __iomem *addr, const void *data, int bytelen);
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void __raw_writesw(volatile void __iomem *addr, const void *data, int wordlen);
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void __raw_writesl(volatile void __iomem *addr, const void *data, int longlen);
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void __raw_readsb(const volatile void __iomem *addr, void *data, int bytelen);
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void __raw_readsw(const volatile void __iomem *addr, void *data, int wordlen);
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void __raw_readsl(const volatile void __iomem *addr, void *data, int longlen);
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#if __LINUX_ARM_ARCH__ < 6
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/*
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* Half-word accesses are problematic with RiscPC due to limitations of
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* the bus. Rather than special-case the machine, just let the compiler
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* generate the access for CPUs prior to ARMv6.
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*/
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#define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
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#define __raw_writew(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
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#else
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/*
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* When running under a hypervisor, we want to avoid I/O accesses with
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* writeback addressing modes as these incur a significant performance
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* overhead (the address generation must be emulated in software).
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*/
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#define __raw_writew __raw_writew
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static inline void __raw_writew(u16 val, volatile void __iomem *addr)
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{
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asm volatile("strh %1, %0"
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: : "Q" (*(volatile u16 __force *)addr), "r" (val));
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}
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#define __raw_readw __raw_readw
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static inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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u16 val;
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asm volatile("ldrh %0, %1"
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: "=r" (val)
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: "Q" (*(volatile u16 __force *)addr));
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return val;
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}
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#endif
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#define __raw_writeb __raw_writeb
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static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
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{
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asm volatile("strb %1, %0"
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: : "Qo" (*(volatile u8 __force *)addr), "r" (val));
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}
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#define __raw_writel __raw_writel
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static inline void __raw_writel(u32 val, volatile void __iomem *addr)
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{
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asm volatile("str %1, %0"
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: : "Qo" (*(volatile u32 __force *)addr), "r" (val));
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}
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#define __raw_readb __raw_readb
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static inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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u8 val;
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asm volatile("ldrb %0, %1"
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: "=r" (val)
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: "Qo" (*(volatile u8 __force *)addr));
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return val;
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}
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#define __raw_readl __raw_readl
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static inline u32 __raw_readl(const volatile void __iomem *addr)
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{
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u32 val;
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asm volatile("ldr %0, %1"
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: "=r" (val)
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: "Qo" (*(volatile u32 __force *)addr));
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return val;
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}
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/*
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* Architecture ioremap implementation.
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*/
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#define MT_DEVICE 0
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#define MT_DEVICE_NONSHARED 1
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#define MT_DEVICE_CACHED 2
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#define MT_DEVICE_WC 3
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/*
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* types 4 onwards can be found in asm/mach/map.h and are undefined
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* for ioremap
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*/
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/*
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* __arm_ioremap takes CPU physical address.
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* __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
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* The _caller variety takes a __builtin_return_address(0) value for
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* /proc/vmalloc to use - and should only be used in non-inline functions.
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*/
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extern void __iomem *__arm_ioremap_caller(phys_addr_t, size_t, unsigned int,
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void *);
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extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
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extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached);
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extern void __iounmap(volatile void __iomem *addr);
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extern void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t,
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unsigned int, void *);
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extern void (*arch_iounmap)(volatile void __iomem *);
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/*
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* Bad read/write accesses...
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*/
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extern void __readwrite_bug(const char *fn);
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/*
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* A typesafe __io() helper
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*/
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static inline void __iomem *__typesafe_io(unsigned long addr)
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{
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return (void __iomem *)addr;
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}
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#define IOMEM(x) ((void __force __iomem *)(x))
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/* IO barriers */
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#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
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#include <asm/barrier.h>
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#define __iormb() rmb()
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#define __iowmb() wmb()
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#else
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#define __iormb() do { } while (0)
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#define __iowmb() do { } while (0)
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#endif
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/* PCI fixed i/o mapping */
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#define PCI_IO_VIRT_BASE 0xfee00000
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#define PCI_IOBASE ((void __iomem *)PCI_IO_VIRT_BASE)
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#if defined(CONFIG_PCI)
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void pci_ioremap_set_mem_type(int mem_type);
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#else
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static inline void pci_ioremap_set_mem_type(int mem_type) {}
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#endif
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extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
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/*
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* PCI configuration space mapping function.
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*
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* The PCI specification does not allow configuration write
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* transactions to be posted. Add an arch specific
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* pci_remap_cfgspace() definition that is implemented
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* through strongly ordered memory mappings.
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*/
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#define pci_remap_cfgspace pci_remap_cfgspace
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void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size);
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/*
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* Now, pick up the machine-defined IO definitions
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*/
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#ifdef CONFIG_NEED_MACH_IO_H
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#include <mach/io.h>
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#elif defined(CONFIG_PCI)
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#define IO_SPACE_LIMIT ((resource_size_t)0xfffff)
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#define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
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#else
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#define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT)
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#endif
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/*
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* This is the limit of PC card/PCI/ISA IO space, which is by default
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* 64K if we have PC card, PCI or ISA support. Otherwise, default to
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* zero to prevent ISA/PCI drivers claiming IO space (and potentially
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* oopsing.)
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*
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* Only set this larger if you really need inb() et.al. to operate over
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* a larger address space. Note that SOC_COMMON ioremaps each sockets
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* IO space area, and so inb() et.al. must be defined to operate as per
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* readb() et.al. on such platforms.
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*/
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#ifndef IO_SPACE_LIMIT
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#if defined(CONFIG_PCMCIA_SOC_COMMON) || defined(CONFIG_PCMCIA_SOC_COMMON_MODULE)
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#define IO_SPACE_LIMIT ((resource_size_t)0xffffffff)
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#elif defined(CONFIG_PCI) || defined(CONFIG_ISA) || defined(CONFIG_PCCARD)
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#define IO_SPACE_LIMIT ((resource_size_t)0xffff)
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#else
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#define IO_SPACE_LIMIT ((resource_size_t)0)
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#endif
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#endif
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/*
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* IO port access primitives
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* -------------------------
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*
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* The ARM doesn't have special IO access instructions; all IO is memory
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* mapped. Note that these are defined to perform little endian accesses
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* only. Their primary purpose is to access PCI and ISA peripherals.
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*
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* Note that for a big endian machine, this implies that the following
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* big endian mode connectivity is in place, as described by numerous
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* ARM documents:
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*
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* PCI: D0-D7 D8-D15 D16-D23 D24-D31
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* ARM: D24-D31 D16-D23 D8-D15 D0-D7
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*
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* The machine specific io.h include defines __io to translate an "IO"
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* address to a memory address.
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*
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* Note that we prevent GCC re-ordering or caching values in expressions
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* by introducing sequence points into the in*() definitions. Note that
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* __raw_* do not guarantee this behaviour.
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*
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* The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
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*/
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#ifdef __io
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#define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); })
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#define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \
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cpu_to_le16(v),__io(p)); })
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#define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \
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cpu_to_le32(v),__io(p)); })
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#define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; })
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#define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \
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__raw_readw(__io(p))); __iormb(); __v; })
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#define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \
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__raw_readl(__io(p))); __iormb(); __v; })
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#define outsb(p,d,l) __raw_writesb(__io(p),d,l)
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#define outsw(p,d,l) __raw_writesw(__io(p),d,l)
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#define outsl(p,d,l) __raw_writesl(__io(p),d,l)
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#define insb(p,d,l) __raw_readsb(__io(p),d,l)
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#define insw(p,d,l) __raw_readsw(__io(p),d,l)
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#define insl(p,d,l) __raw_readsl(__io(p),d,l)
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#endif
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/*
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* String version of IO memory access ops:
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*/
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extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
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extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
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extern void _memset_io(volatile void __iomem *, int, size_t);
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#define mmiowb()
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/*
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* Memory access primitives
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* ------------------------
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*
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* These perform PCI memory accesses via an ioremap region. They don't
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* take an address as such, but a cookie.
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*
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* Again, these are defined to perform little endian accesses. See the
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* IO port primitives for more information.
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*/
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#ifndef readl
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#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
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#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
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__raw_readw(c)); __r; })
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#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
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__raw_readl(c)); __r; })
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#define writeb_relaxed(v,c) __raw_writeb(v,c)
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#define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
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#define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
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#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
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#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
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#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
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#define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
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#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
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#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
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#define readsb(p,d,l) __raw_readsb(p,d,l)
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#define readsw(p,d,l) __raw_readsw(p,d,l)
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#define readsl(p,d,l) __raw_readsl(p,d,l)
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#define writesb(p,d,l) __raw_writesb(p,d,l)
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#define writesw(p,d,l) __raw_writesw(p,d,l)
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#define writesl(p,d,l) __raw_writesl(p,d,l)
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#ifndef __ARMBE__
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static inline void memset_io(volatile void __iomem *dst, unsigned c,
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size_t count)
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{
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extern void mmioset(void *, unsigned int, size_t);
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mmioset((void __force *)dst, c, count);
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}
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#define memset_io(dst,c,count) memset_io(dst,c,count)
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static inline void memcpy_fromio(void *to, const volatile void __iomem *from,
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size_t count)
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{
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extern void mmiocpy(void *, const void *, size_t);
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mmiocpy(to, (const void __force *)from, count);
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}
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#define memcpy_fromio(to,from,count) memcpy_fromio(to,from,count)
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static inline void memcpy_toio(volatile void __iomem *to, const void *from,
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size_t count)
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{
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extern void mmiocpy(void *, const void *, size_t);
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mmiocpy((void __force *)to, from, count);
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}
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#define memcpy_toio(to,from,count) memcpy_toio(to,from,count)
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#else
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#define memset_io(c,v,l) _memset_io(c,(v),(l))
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#define memcpy_fromio(a,c,l) _memcpy_fromio((a),c,(l))
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#define memcpy_toio(c,a,l) _memcpy_toio(c,(a),(l))
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#endif
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#endif /* readl */
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/*
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* ioremap() and friends.
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*
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* ioremap() takes a resource address, and size. Due to the ARM memory
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* types, it is important to use the correct ioremap() function as each
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* mapping has specific properties.
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*
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* Function Memory type Cacheability Cache hint
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* ioremap() Device n/a n/a
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* ioremap_nocache() Device n/a n/a
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* ioremap_cache() Normal Writeback Read allocate
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* ioremap_wc() Normal Non-cacheable n/a
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* ioremap_wt() Normal Non-cacheable n/a
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*
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* All device mappings have the following properties:
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* - no access speculation
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* - no repetition (eg, on return from an exception)
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* - number, order and size of accesses are maintained
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* - unaligned accesses are "unpredictable"
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* - writes may be delayed before they hit the endpoint device
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*
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* ioremap_nocache() is the same as ioremap() as there are too many device
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* drivers using this for device registers, and documentation which tells
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* people to use it for such for this to be any different. This is not a
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* safe fallback for memory-like mappings, or memory regions where the
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* compiler may generate unaligned accesses - eg, via inlining its own
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* memcpy.
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*
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* All normal memory mappings have the following properties:
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* - reads can be repeated with no side effects
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* - repeated reads return the last value written
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* - reads can fetch additional locations without side effects
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* - writes can be repeated (in certain cases) with no side effects
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* - writes can be merged before accessing the target
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* - unaligned accesses can be supported
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* - ordering is not guaranteed without explicit dependencies or barrier
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* instructions
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* - writes may be delayed before they hit the endpoint memory
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*
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* The cache hint is only a performance hint: CPUs may alias these hints.
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* Eg, a CPU not implementing read allocate but implementing write allocate
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* will provide a write allocate mapping instead.
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*/
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void __iomem *ioremap(resource_size_t res_cookie, size_t size);
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#define ioremap ioremap
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#define ioremap_nocache ioremap
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/*
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* Do not use ioremap_cache for mapping memory. Use memremap instead.
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*/
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void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size);
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#define ioremap_cache ioremap_cache
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/*
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* Do not use ioremap_cached in new code. Provided for the benefit of
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* the pxa2xx-flash MTD driver only.
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*/
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void __iomem *ioremap_cached(resource_size_t res_cookie, size_t size);
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void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size);
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#define ioremap_wc ioremap_wc
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#define ioremap_wt ioremap_wc
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void iounmap(volatile void __iomem *iomem_cookie);
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#define iounmap iounmap
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void *arch_memremap_wb(phys_addr_t phys_addr, size_t size);
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#define arch_memremap_wb arch_memremap_wb
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/*
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* io{read,write}{16,32}be() macros
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*/
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#define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
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#define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
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#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
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#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
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#ifndef ioport_map
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#define ioport_map ioport_map
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extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
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#endif
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#ifndef ioport_unmap
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|
#define ioport_unmap ioport_unmap
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|
extern void ioport_unmap(void __iomem *addr);
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|
#endif
|
|
|
|
struct pci_dev;
|
|
|
|
#define pci_iounmap pci_iounmap
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|
extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
|
|
|
|
/*
|
|
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
|
|
* access
|
|
*/
|
|
#define xlate_dev_mem_ptr(p) __va(p)
|
|
|
|
/*
|
|
* Convert a virtual cached pointer to an uncached pointer
|
|
*/
|
|
#define xlate_dev_kmem_ptr(p) p
|
|
|
|
#include <asm-generic/io.h>
|
|
|
|
/*
|
|
* can the hardware map this into one segment or not, given no other
|
|
* constraints.
|
|
*/
|
|
#define BIOVEC_MERGEABLE(vec1, vec2) \
|
|
((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
|
|
|
|
struct bio_vec;
|
|
extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
|
|
const struct bio_vec *vec2);
|
|
#define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \
|
|
(__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \
|
|
(!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))
|
|
|
|
#ifdef CONFIG_MMU
|
|
#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
|
|
extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
|
|
extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
|
|
extern int devmem_is_allowed(unsigned long pfn);
|
|
#endif
|
|
|
|
/*
|
|
* Register ISA memory and port locations for glibc iopl/inb/outb
|
|
* emulation.
|
|
*/
|
|
extern void register_isa_ports(unsigned int mmio, unsigned int io,
|
|
unsigned int io_shift);
|
|
|
|
#endif /* __KERNEL__ */
|
|
#endif /* __ASM_ARM_IO_H */
|