372 lines
8.8 KiB
C
372 lines
8.8 KiB
C
/*
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef __ARM_KVM_MMU_H__
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#define __ARM_KVM_MMU_H__
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#include <asm/memory.h>
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#include <asm/page.h>
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/*
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* We directly use the kernel VA for the HYP, as we can directly share
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* the mapping (HTTBR "covers" TTBR1).
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*/
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#define kern_hyp_va(kva) (kva)
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/* Contrary to arm64, there is no need to generate a PC-relative address */
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#define hyp_symbol_addr(s) \
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({ \
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typeof(s) *addr = &(s); \
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addr; \
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})
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/*
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* KVM_MMU_CACHE_MIN_PAGES is the number of stage2 page table translation levels.
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*/
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#define KVM_MMU_CACHE_MIN_PAGES 2
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#ifndef __ASSEMBLY__
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#include <linux/highmem.h>
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#include <asm/cacheflush.h>
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#include <asm/cputype.h>
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#include <asm/kvm_hyp.h>
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#include <asm/pgalloc.h>
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#include <asm/stage2_pgtable.h>
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/* Ensure compatibility with arm64 */
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#define VA_BITS 32
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int create_hyp_mappings(void *from, void *to, pgprot_t prot);
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int create_hyp_io_mappings(phys_addr_t phys_addr, size_t size,
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void __iomem **kaddr,
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void __iomem **haddr);
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int create_hyp_exec_mappings(phys_addr_t phys_addr, size_t size,
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void **haddr);
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void free_hyp_pgds(void);
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void stage2_unmap_vm(struct kvm *kvm);
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int kvm_alloc_stage2_pgd(struct kvm *kvm);
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void kvm_free_stage2_pgd(struct kvm *kvm);
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int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
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phys_addr_t pa, unsigned long size, bool writable);
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int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
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void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
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phys_addr_t kvm_mmu_get_httbr(void);
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phys_addr_t kvm_get_idmap_vector(void);
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int kvm_mmu_init(void);
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void kvm_clear_hyp_idmap(void);
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#define kvm_mk_pmd(ptep) __pmd(__pa(ptep) | PMD_TYPE_TABLE)
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#define kvm_mk_pud(pmdp) __pud(__pa(pmdp) | PMD_TYPE_TABLE)
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#define kvm_mk_pgd(pudp) ({ BUILD_BUG(); 0; })
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static inline pte_t kvm_s2pte_mkwrite(pte_t pte)
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{
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pte_val(pte) |= L_PTE_S2_RDWR;
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return pte;
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}
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static inline pmd_t kvm_s2pmd_mkwrite(pmd_t pmd)
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{
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pmd_val(pmd) |= L_PMD_S2_RDWR;
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return pmd;
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}
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static inline pte_t kvm_s2pte_mkexec(pte_t pte)
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{
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pte_val(pte) &= ~L_PTE_XN;
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return pte;
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}
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static inline pmd_t kvm_s2pmd_mkexec(pmd_t pmd)
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{
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pmd_val(pmd) &= ~PMD_SECT_XN;
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return pmd;
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}
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static inline void kvm_set_s2pte_readonly(pte_t *pte)
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{
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pte_val(*pte) = (pte_val(*pte) & ~L_PTE_S2_RDWR) | L_PTE_S2_RDONLY;
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}
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static inline bool kvm_s2pte_readonly(pte_t *pte)
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{
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return (pte_val(*pte) & L_PTE_S2_RDWR) == L_PTE_S2_RDONLY;
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}
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static inline bool kvm_s2pte_exec(pte_t *pte)
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{
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return !(pte_val(*pte) & L_PTE_XN);
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}
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static inline void kvm_set_s2pmd_readonly(pmd_t *pmd)
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{
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pmd_val(*pmd) = (pmd_val(*pmd) & ~L_PMD_S2_RDWR) | L_PMD_S2_RDONLY;
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}
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static inline bool kvm_s2pmd_readonly(pmd_t *pmd)
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{
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return (pmd_val(*pmd) & L_PMD_S2_RDWR) == L_PMD_S2_RDONLY;
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}
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static inline bool kvm_s2pmd_exec(pmd_t *pmd)
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{
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return !(pmd_val(*pmd) & PMD_SECT_XN);
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}
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static inline bool kvm_page_empty(void *ptr)
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{
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struct page *ptr_page = virt_to_page(ptr);
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return page_count(ptr_page) == 1;
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}
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#define kvm_pte_table_empty(kvm, ptep) kvm_page_empty(ptep)
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#define kvm_pmd_table_empty(kvm, pmdp) kvm_page_empty(pmdp)
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#define kvm_pud_table_empty(kvm, pudp) false
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#define hyp_pte_table_empty(ptep) kvm_page_empty(ptep)
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#define hyp_pmd_table_empty(pmdp) kvm_page_empty(pmdp)
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#define hyp_pud_table_empty(pudp) false
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struct kvm;
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#define kvm_flush_dcache_to_poc(a,l) __cpuc_flush_dcache_area((a), (l))
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static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
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{
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return (vcpu_cp15(vcpu, c1_SCTLR) & 0b101) == 0b101;
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}
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static inline void __clean_dcache_guest_page(kvm_pfn_t pfn, unsigned long size)
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{
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/*
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* Clean the dcache to the Point of Coherency.
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*
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* We need to do this through a kernel mapping (using the
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* user-space mapping has proved to be the wrong
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* solution). For that, we need to kmap one page at a time,
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* and iterate over the range.
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*/
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VM_BUG_ON(size & ~PAGE_MASK);
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while (size) {
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void *va = kmap_atomic_pfn(pfn);
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kvm_flush_dcache_to_poc(va, PAGE_SIZE);
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size -= PAGE_SIZE;
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pfn++;
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kunmap_atomic(va);
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}
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}
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static inline void __invalidate_icache_guest_page(kvm_pfn_t pfn,
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unsigned long size)
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{
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u32 iclsz;
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/*
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* If we are going to insert an instruction page and the icache is
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* either VIPT or PIPT, there is a potential problem where the host
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* (or another VM) may have used the same page as this guest, and we
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* read incorrect data from the icache. If we're using a PIPT cache,
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* we can invalidate just that page, but if we are using a VIPT cache
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* we need to invalidate the entire icache - damn shame - as written
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* in the ARM ARM (DDI 0406C.b - Page B3-1393).
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*
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* VIVT caches are tagged using both the ASID and the VMID and doesn't
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* need any kind of flushing (DDI 0406C.b - Page B3-1392).
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*/
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VM_BUG_ON(size & ~PAGE_MASK);
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if (icache_is_vivt_asid_tagged())
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return;
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if (!icache_is_pipt()) {
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/* any kind of VIPT cache */
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__flush_icache_all();
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return;
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}
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/*
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* CTR IminLine contains Log2 of the number of words in the
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* cache line, so we can get the number of words as
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* 2 << (IminLine - 1). To get the number of bytes, we
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* multiply by 4 (the number of bytes in a 32-bit word), and
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* get 4 << (IminLine).
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*/
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iclsz = 4 << (read_cpuid(CPUID_CACHETYPE) & 0xf);
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while (size) {
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void *va = kmap_atomic_pfn(pfn);
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void *end = va + PAGE_SIZE;
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void *addr = va;
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do {
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write_sysreg(addr, ICIMVAU);
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addr += iclsz;
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} while (addr < end);
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dsb(ishst);
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isb();
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size -= PAGE_SIZE;
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pfn++;
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kunmap_atomic(va);
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}
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/* Check if we need to invalidate the BTB */
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if ((read_cpuid_ext(CPUID_EXT_MMFR1) >> 28) != 4) {
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write_sysreg(0, BPIALLIS);
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dsb(ishst);
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isb();
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}
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}
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static inline void __kvm_flush_dcache_pte(pte_t pte)
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{
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void *va = kmap_atomic(pte_page(pte));
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kvm_flush_dcache_to_poc(va, PAGE_SIZE);
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kunmap_atomic(va);
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}
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static inline void __kvm_flush_dcache_pmd(pmd_t pmd)
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{
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unsigned long size = PMD_SIZE;
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kvm_pfn_t pfn = pmd_pfn(pmd);
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while (size) {
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void *va = kmap_atomic_pfn(pfn);
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kvm_flush_dcache_to_poc(va, PAGE_SIZE);
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pfn++;
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size -= PAGE_SIZE;
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kunmap_atomic(va);
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}
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}
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static inline void __kvm_flush_dcache_pud(pud_t pud)
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{
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}
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#define kvm_virt_to_phys(x) virt_to_idmap((unsigned long)(x))
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void kvm_set_way_flush(struct kvm_vcpu *vcpu);
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void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled);
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static inline bool __kvm_cpu_uses_extended_idmap(void)
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{
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return false;
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}
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static inline unsigned long __kvm_idmap_ptrs_per_pgd(void)
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{
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return PTRS_PER_PGD;
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}
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static inline void __kvm_extend_hypmap(pgd_t *boot_hyp_pgd,
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pgd_t *hyp_pgd,
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pgd_t *merged_hyp_pgd,
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unsigned long hyp_idmap_start) { }
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static inline unsigned int kvm_get_vmid_bits(void)
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{
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return 8;
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}
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/*
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* We are not in the kvm->srcu critical section most of the time, so we take
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* the SRCU read lock here. Since we copy the data from the user page, we
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* can immediately drop the lock again.
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*/
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static inline int kvm_read_guest_lock(struct kvm *kvm,
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gpa_t gpa, void *data, unsigned long len)
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{
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int srcu_idx = srcu_read_lock(&kvm->srcu);
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int ret = kvm_read_guest(kvm, gpa, data, len);
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srcu_read_unlock(&kvm->srcu, srcu_idx);
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return ret;
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}
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static inline int kvm_write_guest_lock(struct kvm *kvm, gpa_t gpa,
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const void *data, unsigned long len)
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{
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int srcu_idx = srcu_read_lock(&kvm->srcu);
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int ret = kvm_write_guest(kvm, gpa, data, len);
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srcu_read_unlock(&kvm->srcu, srcu_idx);
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return ret;
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}
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static inline void *kvm_get_hyp_vector(void)
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{
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switch(read_cpuid_part()) {
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#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
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case ARM_CPU_PART_CORTEX_A12:
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case ARM_CPU_PART_CORTEX_A17:
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{
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extern char __kvm_hyp_vector_bp_inv[];
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return kvm_ksym_ref(__kvm_hyp_vector_bp_inv);
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}
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case ARM_CPU_PART_BRAHMA_B15:
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case ARM_CPU_PART_CORTEX_A15:
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{
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extern char __kvm_hyp_vector_ic_inv[];
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return kvm_ksym_ref(__kvm_hyp_vector_ic_inv);
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}
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#endif
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default:
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{
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extern char __kvm_hyp_vector[];
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return kvm_ksym_ref(__kvm_hyp_vector);
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}
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}
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}
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static inline int kvm_map_vectors(void)
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{
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return 0;
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}
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static inline int hyp_map_aux_data(void)
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{
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return 0;
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}
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#define kvm_phys_to_vttbr(addr) (addr)
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#endif /* !__ASSEMBLY__ */
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#endif /* __ARM_KVM_MMU_H__ */
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