330 lines
7 KiB
ArmAsm
330 lines
7 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <asm/assembler.h>
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/asm-uaccess.h>
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.text
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.equ SCTLR_C_BIT, 0x00000004
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.equ SCTLR_I_BIT, 0x00001000
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.equ DCISW, 0x0
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.equ DCCISW, 0x1
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.equ DCCSW, 0x2
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.equ LOC_SHIFT, 24
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.equ CLIDR_FIELD_WIDTH, 3
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.equ LEVEL_SHIFT, 1
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ENTRY(__enable_icache)
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mrs x0, SCTLR_EL1
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orr x0, x0, #SCTLR_I_BIT
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msr SCTLR_EL1, x0
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ret
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ENDPROC(__enable_icache)
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ENTRY(__disable_icache)
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mrs x0, SCTLR_EL1
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bic x0, x0, #SCTLR_I_BIT
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msr SCTLR_EL1, x0
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ret
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ENDPROC(__disable_icache)
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/* might pollute x0 */
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.macro __dis_D
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mrs x0, SCTLR_EL1
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bic x0, x0, #SCTLR_C_BIT
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dsb sy
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msr SCTLR_EL1, x0
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dsb sy
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isb sy
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.endm
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ENTRY(__enable_dcache)
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mrs x0, SCTLR_EL1
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orr x0, x0, #SCTLR_C_BIT
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dsb sy
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msr SCTLR_EL1, x0
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dsb sy
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isb sy
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ret
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ENDPROC(__enable_dcache)
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ENTRY(__disable_dcache)
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mrs x0, SCTLR_EL1
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bic x0, x0, #SCTLR_C_BIT
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dsb sy
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msr SCTLR_EL1, x0
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dsb sy
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isb sy
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ret
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ENDPROC(__disable_dcache)
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ENTRY(__enable_cache)
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mrs x0, SCTLR_EL1
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orr x0, x0, #SCTLR_I_BIT
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orr x0, x0, #SCTLR_C_BIT
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dsb sy
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msr SCTLR_EL1, x0
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dsb sy
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isb sy
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ret
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ENDPROC(__enable_cache)
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ENTRY(__disable_cache)
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mrs x0, SCTLR_EL1
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bic x0, x0, #SCTLR_I_BIT
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bic x0, x0, #SCTLR_C_BIT
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dsb sy
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msr SCTLR_EL1, x0
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dsb sy
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isb sy
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ret
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ENDPROC(__disable_cache)
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/* ---------------------------------------------------------------
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* Data cache operations by set/way to the level specified
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*
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* The main function, do_dcsw_op requires:
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* x0: The operation type (0-2), as defined in arch.h
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* x1: The first cache level to operate on
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* x3: The last cache level to operate on
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* x9: clidr_el1
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* and will carry out the operation on each data cache from level 0
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* to the level in x3 in sequence
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*
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* The dcsw_op macro sets up the x3 and x9 parameters based on
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* clidr_el1 cache information before invoking the main function
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* ---------------------------------------------------------------
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*/
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ENTRY(do_dcsw_op)
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lsl x3, x3, #1
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cbz x3, exit
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sub x1, x1, #1
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lsl x1, x1, #1
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mov x10, x1
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adr x14, dcsw_loop_table
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add x14, x14, x0, lsl #5
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mov x0, x9
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mov w8, #1
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loop:
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add x2, x10, x10, lsr #1
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lsr x1, x0, x2
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and x1, x1, #7
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cmp x1, #2
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b.lt level_done
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msr csselr_el1, x10
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isb
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mrs x1, ccsidr_el1
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and x2, x1, #7
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add x2, x2, #4
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ubfx x4, x1, #3, #10
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clz w5, w4
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lsl w9, w4, w5
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lsl w16, w8, w5
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orr w9, w10, w9
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ubfx w6, w1, #13, #15
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lsl w17, w8, w2
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dsb sy
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br x14
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.macro dcsw_loop _op
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loop2_\_op:
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lsl w7, w6, w2
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loop3_\_op:
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orr w11, w9, w7
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dc \_op, x11
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subs w7, w7, w17
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b.ge loop3_\_op
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subs x9, x9, x16
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b.ge loop2_\_op
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b level_done
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.endm
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level_done:
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add x10, x10, #2
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cmp x3, x10
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b.gt loop
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msr csselr_el1, xzr
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dsb sy
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isb
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exit:
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ret
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ENDPROC(do_dcsw_op)
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dcsw_loop_table:
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dcsw_loop isw
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dcsw_loop cisw
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dcsw_loop csw
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.macro __inner_dcache_all mode
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mov x0, \mode
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mov x1, #1
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mrs x9, clidr_el1
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ubfx x3, x9, #24, #0x7 /* LOC as last cache level */
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b do_dcsw_op
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.endm
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.macro __inner_dcache_L1 mode
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mov x0, \mode
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mov x1, #1
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mov x3, #1
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mrs x9, clidr_el1
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b do_dcsw_op
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.endm
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.macro __inner_dcache_L2 mode
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mov x0, \mode
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mov x1, #2
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mov x3, #2
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mrs x9, clidr_el1
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b do_dcsw_op
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.endm
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.macro __inner_dcache_L1_L2 mode
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mov x0, \mode
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mov x1, #1
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mov x3, #2
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mrs x9, clidr_el1
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b do_dcsw_op
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.endm
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ENTRY(__inner_flush_dcache_all)
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__inner_dcache_all #DCCISW
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ENDPROC(__inner_flush_dcache_all)
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ENTRY(__inner_flush_dcache_L1)
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__inner_dcache_L1 #DCCISW
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ENDPROC(__inner_flush_dcache_L1)
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ENTRY(__inner_flush_dcache_L2)
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__inner_dcache_L2 #DCCISW
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ENDPROC(__inner_flush_dcache_L2)
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ENTRY(__inner_clean_dcache_all)
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__inner_dcache_all #DCCSW
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ENDPROC(__inner_clean_dcache_all)
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ENTRY(__inner_clean_dcache_L1)
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__inner_dcache_L1 #DCCSW
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ENDPROC(__inner_clean_dcache_L1)
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ENTRY(__inner_clean_dcache_L2)
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__inner_dcache_L2 #DCCSW
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ENDPROC(__inner_clean_dcache_L2)
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ENTRY(__inner_inv_dcache_all)
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__inner_dcache_all #DCISW
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ENDPROC(__inner_inv_dcache_all)
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ENTRY(__inner_inv_dcache_L1)
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__inner_dcache_L1 #DCISW
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ENDPROC(__inner_clean_dcache_L1)
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ENTRY(__inner_inv_dcache_L2)
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__inner_dcache_L2 #DCISW
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ENDPROC(__inner_clean_dcache_L2)
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ENTRY(__disable_dcache__inner_flush_dcache_L1)
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__dis_D
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__inner_dcache_L1 #DCCISW
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ENDPROC(__disable_dcache__inner_flush_dcache_L1)
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ENTRY(__disable_dcache__inner_flush_dcache_L1__inner_flush_dcache_L2)
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__dis_D
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__inner_dcache_L1_L2 #DCCISW
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ENDPROC(__disable_dcache__inner_flush_dcache_L1__inner_flush_dcache_L2)
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ENTRY(__disable_dcache__inner_clean_dcache_L1__inner_clean_dcache_L2)
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__dis_D
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__inner_dcache_L1_L2 #DCCSW
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ENDPROC(__disable_dcache__inner_clean_dcache_L1__inner_clean_dcache_L2)
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ENTRY(dis_D_inner_fL1L2)
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__dis_D
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/* since we need to do different operations for L1/L2,
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and our current implementation would jump from
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do_dcsw_op to caller(who invokes the last bl) directly,
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we need to construct stack frame by ourself here.
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We use two caller-saved registers, x12 & x13, to save lr & sp,
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to prevent any memory access during cache operation
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NOTICE: any macro or function MUST not corrupt x12 & x13 here
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*/
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mov x12, x29
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mov x13, x30
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mov x29, sp
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bl __inner_flush_dcache_L1
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mov x29, x12
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mov x30, x13
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__inner_dcache_L2 #DCCSW
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ENDPROC(dis_D_inner_fL1L2)
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ENTRY(dis_D_inner_flush_all)
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__dis_D
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__inner_dcache_all #DCCISW
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ENDPROC(dis_D_inner_flush_all)
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/*
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* __xxxx_dcache_user_range(start,size)
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*
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* Ensure that any D-cache lines for the interval [start, start+size)
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* are cleaned or/and invalidated to the PoC.
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*
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* - start - virtual start address of region (EL0/EL1)
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* - size - size in question
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*/
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ENTRY(__flush_dcache_user_area)
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uaccess_ttbr0_enable x2, x3, x4
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dcache_by_line_op civac, sy, x0, x1, x2, x3
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uaccess_ttbr0_disable x1, x2
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ret
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ENDPROC(__flush_dcache_user_area)
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ENTRY(__clean_dcache_user_area)
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uaccess_ttbr0_enable x2, x3, x4
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dcache_by_line_op cvac, sy, x0, x1, x2, x3
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uaccess_ttbr0_disable x1, x2
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ret
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ENDPROC(__clean_dcache_user_area)
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ENTRY(__inval_dcache_user_area)
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add x1, x1, x0
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uaccess_ttbr0_enable x2, x3, x4
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dcache_line_size x2, x3
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sub x3, x2, #1
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tst x1, x3 // end cache line aligned?
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bic x1, x1, x3
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b.eq 1f
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dc civac, x1 // clean & invalidate D / U line
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1: tst x0, x3 // start cache line aligned?
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bic x0, x0, x3
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b.eq 2f
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dc civac, x0 // clean & invalidate D / U line
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b 3f
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2: dc civac, x0 // invalidate D / U line
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3: add x0, x0, x2
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cmp x0, x1
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b.lo 2b
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dsb sy
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uaccess_ttbr0_disable x1, x2
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ret
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ENDPROC(__inval_dcache_user_area)
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