161 lines
4.2 KiB
C
161 lines
4.2 KiB
C
/*
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* OpenRISC Linux
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*
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* Linux architectural port borrowing liberally from similar works of
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* others. All original copyrights apply as per the original source
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* declaration.
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*
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* Modifications for the OpenRISC architecture:
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* Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
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* Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* DMA mapping callbacks...
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* As alloc_coherent is the only DMA callback being used currently, that's
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* the only thing implemented properly. The rest need looking into...
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*/
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#include <linux/dma-noncoherent.h>
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#include <asm/cpuinfo.h>
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#include <asm/spr_defs.h>
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#include <asm/tlbflush.h>
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static int
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page_set_nocache(pte_t *pte, unsigned long addr,
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unsigned long next, struct mm_walk *walk)
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{
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unsigned long cl;
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struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
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pte_val(*pte) |= _PAGE_CI;
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/*
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* Flush the page out of the TLB so that the new page flags get
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* picked up next time there's an access
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*/
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flush_tlb_page(NULL, addr);
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/* Flush page out of dcache */
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for (cl = __pa(addr); cl < __pa(next); cl += cpuinfo->dcache_block_size)
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mtspr(SPR_DCBFR, cl);
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return 0;
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}
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static int
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page_clear_nocache(pte_t *pte, unsigned long addr,
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unsigned long next, struct mm_walk *walk)
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{
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pte_val(*pte) &= ~_PAGE_CI;
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/*
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* Flush the page out of the TLB so that the new page flags get
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* picked up next time there's an access
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*/
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flush_tlb_page(NULL, addr);
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return 0;
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}
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/*
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* Alloc "coherent" memory, which for OpenRISC means simply uncached.
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*
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* This function effectively just calls __get_free_pages, sets the
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* cache-inhibit bit on those pages, and makes sure that the pages are
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* flushed out of the cache before they are used.
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*
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* If the NON_CONSISTENT attribute is set, then this function just
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* returns "normal", cachable memory.
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*
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* There are additional flags WEAK_ORDERING and WRITE_COMBINE to take
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* into consideration here, too. All current known implementations of
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* the OR1K support only strongly ordered memory accesses, so that flag
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* is being ignored for now; uncached but write-combined memory is a
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* missing feature of the OR1K.
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*/
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void *
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arch_dma_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle,
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gfp_t gfp, unsigned long attrs)
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{
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unsigned long va;
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void *page;
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struct mm_walk walk = {
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.pte_entry = page_set_nocache,
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.mm = &init_mm
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};
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page = alloc_pages_exact(size, gfp);
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if (!page)
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return NULL;
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/* This gives us the real physical address of the first page. */
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*dma_handle = __pa(page);
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va = (unsigned long)page;
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if ((attrs & DMA_ATTR_NON_CONSISTENT) == 0) {
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/*
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* We need to iterate through the pages, clearing the dcache for
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* them and setting the cache-inhibit bit.
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*/
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if (walk_page_range(va, va + size, &walk)) {
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free_pages_exact(page, size);
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return NULL;
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}
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}
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return (void *)va;
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}
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void
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arch_dma_free(struct device *dev, size_t size, void *vaddr,
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dma_addr_t dma_handle, unsigned long attrs)
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{
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unsigned long va = (unsigned long)vaddr;
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struct mm_walk walk = {
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.pte_entry = page_clear_nocache,
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.mm = &init_mm
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};
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if ((attrs & DMA_ATTR_NON_CONSISTENT) == 0) {
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/* walk_page_range shouldn't be able to fail here */
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WARN_ON(walk_page_range(va, va + size, &walk));
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}
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free_pages_exact(vaddr, size);
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}
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void arch_sync_dma_for_device(struct device *dev, phys_addr_t addr, size_t size,
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enum dma_data_direction dir)
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{
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unsigned long cl;
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struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
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switch (dir) {
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case DMA_TO_DEVICE:
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/* Flush the dcache for the requested range */
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for (cl = addr; cl < addr + size;
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cl += cpuinfo->dcache_block_size)
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mtspr(SPR_DCBFR, cl);
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break;
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case DMA_FROM_DEVICE:
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/* Invalidate the dcache for the requested range */
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for (cl = addr; cl < addr + size;
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cl += cpuinfo->dcache_block_size)
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mtspr(SPR_DCBIR, cl);
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break;
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default:
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/*
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* NOTE: If dir == DMA_BIDIRECTIONAL then there's no need to
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* flush nor invalidate the cache here as the area will need
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* to be manually synced anyway.
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*/
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break;
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}
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}
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