139 lines
3.4 KiB
C
139 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt6853-clk.h>
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#define MT_CLKMGR_MODULE_INIT 0
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#define MT_CCF_BRINGUP 1
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#define INV_OFS -1
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/* get spm power status struct to register inside clk_data */
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static struct pwr_status pwr_stat = GATE_PWR_STAT(INV_OFS,
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INV_OFS, 0x0178, BIT(5), BIT(5));
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static const struct mtk_gate_regs apuc_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_APUC(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &apuc_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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.pwr_stat = &pwr_stat, \
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}
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static const struct mtk_gate apuc_clks[] = {
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GATE_APUC(CLK_APUC_APU, "apuc_apu",
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"dsp_ck"/* parent */, 0),
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GATE_APUC(CLK_APUC_AHB, "apuc_ahb",
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"dsp_ck"/* parent */, 1),
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GATE_APUC(CLK_APUC_AXI, "apuc_axi",
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"dsp_ck"/* parent */, 2),
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GATE_APUC(CLK_APUC_ISP, "apuc_isp",
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"dsp_ck"/* parent */, 3),
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GATE_APUC(CLK_APUC_CAM_ADL, "apuc_cam_adl",
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"dsp_ck"/* parent */, 4),
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GATE_APUC(CLK_APUC_IMG_ADL, "apuc_img_adl",
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"dsp_ck"/* parent */, 5),
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GATE_APUC(CLK_APUC_EMI_26M, "apuc_emi_26m",
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"dsp_ck"/* parent */, 6),
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GATE_APUC(CLK_APUC_VPU_UDI, "apuc_vpu_udi",
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"dsp_ck"/* parent */, 7),
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GATE_APUC(CLK_APUC_EDMA_0, "apuc_edma_0",
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"dsp_ck"/* parent */, 8),
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GATE_APUC(CLK_APUC_EDMA_1, "apuc_edma_1",
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"dsp_ck"/* parent */, 9),
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GATE_APUC(CLK_APUC_EDMAL_0, "apuc_edmal_0",
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"dsp_ck"/* parent */, 10),
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GATE_APUC(CLK_APUC_EDMAL_1, "apuc_edmal_1",
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"dsp_ck"/* parent */, 11),
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GATE_APUC(CLK_APUC_MNOC, "apuc_mnoc",
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"dsp_ck"/* parent */, 12),
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GATE_APUC(CLK_APUC_TCM, "apuc_tcm",
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"dsp_ck"/* parent */, 13),
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GATE_APUC(CLK_APUC_MD32, "apuc_md32",
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"dsp_ck"/* parent */, 14),
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GATE_APUC(CLK_APUC_IOMMU_0, "apuc_iommu_0",
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"dsp_ck"/* parent */, 15),
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GATE_APUC(CLK_APUC_MD32_32K, "apuc_md32_32k",
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"dsp_ck"/* parent */, 17),
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};
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static int clk_mt6853_apuc_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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int r;
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struct device_node *node = pdev->dev.of_node;
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#if MT_CCF_BRINGUP
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pr_notice("%s init begin\n", __func__);
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#endif
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clk_data = mtk_alloc_clk_data(CLK_APUC_NR_CLK);
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mtk_clk_register_gates(node, apuc_clks, ARRAY_SIZE(apuc_clks),
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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#if MT_CCF_BRINGUP
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pr_notice("%s init end\n", __func__);
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#endif
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return r;
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}
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static const struct of_device_id of_match_clk_mt6853_apuc[] = {
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{ .compatible = "mediatek,mt6853-apu_conn", },
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{}
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};
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#if MT_CLKMGR_MODULE_INIT
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static struct platform_driver clk_mt6853_apuc_drv = {
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.probe = clk_mt6853_apuc_probe,
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.driver = {
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.name = "clk-mt6853-apuc",
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.of_match_table = of_match_clk_mt6853_apuc,
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},
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};
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builtin_platform_driver(clk_mt6853_apuc_drv);
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#else
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static struct platform_driver clk_mt6853_apuc_drv = {
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.probe = clk_mt6853_apuc_probe,
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.driver = {
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.name = "clk-mt6853-apuc",
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.of_match_table = of_match_clk_mt6853_apuc,
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},
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};
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static int __init clk_mt6853_apuc_platform_init(void)
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{
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return platform_driver_register(&clk_mt6853_apuc_drv);
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}
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arch_initcall(clk_mt6853_apuc_platform_init);
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#endif /* MT_CLKMGR_MODULE_INIT */
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