159 lines
4 KiB
C
159 lines
4 KiB
C
/*
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* Marvell Armada 39x SoC clocks
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*
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* Copyright (C) 2015 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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* Andrew Lunn <andrew@lunn.ch>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include "common.h"
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/*
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* SARL[14:10] : Ratios between CPU, NBCLK, HCLK and DCLK.
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*
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* SARL[15] : TCLK frequency
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* 0 = 250 MHz
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* 1 = 200 MHz
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*
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* SARH[0] : Reference clock frequency
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* 0 = 25 Mhz
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* 1 = 40 Mhz
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*/
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#define SARL 0
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#define SARL_A390_TCLK_FREQ_OPT 15
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#define SARL_A390_TCLK_FREQ_OPT_MASK 0x1
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#define SARL_A390_CPU_DDR_L2_FREQ_OPT 10
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#define SARL_A390_CPU_DDR_L2_FREQ_OPT_MASK 0x1F
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#define SARH 4
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#define SARH_A390_REFCLK_FREQ BIT(0)
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static const u32 armada_39x_tclk_frequencies[] __initconst = {
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250000000,
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200000000,
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};
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static u32 __init armada_39x_get_tclk_freq(void __iomem *sar)
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{
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u8 tclk_freq_select;
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tclk_freq_select = ((readl(sar + SARL) >> SARL_A390_TCLK_FREQ_OPT) &
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SARL_A390_TCLK_FREQ_OPT_MASK);
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return armada_39x_tclk_frequencies[tclk_freq_select];
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}
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static const u32 armada_39x_cpu_frequencies[] __initconst = {
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[0x0] = 666 * 1000 * 1000,
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[0x2] = 800 * 1000 * 1000,
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[0x3] = 800 * 1000 * 1000,
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[0x4] = 1066 * 1000 * 1000,
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[0x5] = 1066 * 1000 * 1000,
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[0x6] = 1200 * 1000 * 1000,
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[0x8] = 1332 * 1000 * 1000,
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[0xB] = 1600 * 1000 * 1000,
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[0xC] = 1600 * 1000 * 1000,
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[0x12] = 1800 * 1000 * 1000,
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[0x1E] = 1800 * 1000 * 1000,
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};
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static u32 __init armada_39x_get_cpu_freq(void __iomem *sar)
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{
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u8 cpu_freq_select;
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cpu_freq_select = ((readl(sar + SARL) >> SARL_A390_CPU_DDR_L2_FREQ_OPT) &
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SARL_A390_CPU_DDR_L2_FREQ_OPT_MASK);
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if (cpu_freq_select >= ARRAY_SIZE(armada_39x_cpu_frequencies)) {
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pr_err("Selected CPU frequency (%d) unsupported\n",
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cpu_freq_select);
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return 0;
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}
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return armada_39x_cpu_frequencies[cpu_freq_select];
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}
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enum { A390_CPU_TO_NBCLK, A390_CPU_TO_HCLK, A390_CPU_TO_DCLK };
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static const struct coreclk_ratio armada_39x_coreclk_ratios[] __initconst = {
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{ .id = A390_CPU_TO_NBCLK, .name = "nbclk" },
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{ .id = A390_CPU_TO_HCLK, .name = "hclk" },
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{ .id = A390_CPU_TO_DCLK, .name = "dclk" },
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};
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static void __init armada_39x_get_clk_ratio(
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void __iomem *sar, int id, int *mult, int *div)
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{
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switch (id) {
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case A390_CPU_TO_NBCLK:
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*mult = 1;
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*div = 2;
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break;
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case A390_CPU_TO_HCLK:
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*mult = 1;
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*div = 4;
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break;
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case A390_CPU_TO_DCLK:
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*mult = 1;
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*div = 2;
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break;
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}
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}
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static u32 __init armada_39x_refclk_ratio(void __iomem *sar)
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{
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if (readl(sar + SARH) & SARH_A390_REFCLK_FREQ)
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return 40 * 1000 * 1000;
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else
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return 25 * 1000 * 1000;
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}
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static const struct coreclk_soc_desc armada_39x_coreclks = {
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.get_tclk_freq = armada_39x_get_tclk_freq,
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.get_cpu_freq = armada_39x_get_cpu_freq,
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.get_clk_ratio = armada_39x_get_clk_ratio,
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.get_refclk_freq = armada_39x_refclk_ratio,
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.ratios = armada_39x_coreclk_ratios,
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.num_ratios = ARRAY_SIZE(armada_39x_coreclk_ratios),
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};
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static void __init armada_39x_coreclk_init(struct device_node *np)
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{
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mvebu_coreclk_setup(np, &armada_39x_coreclks);
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}
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CLK_OF_DECLARE(armada_39x_core_clk, "marvell,armada-390-core-clock",
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armada_39x_coreclk_init);
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/*
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* Clock Gating Control
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*/
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static const struct clk_gating_soc_desc armada_39x_gating_desc[] __initconst = {
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{ "pex1", NULL, 5 },
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{ "pex2", NULL, 6 },
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{ "pex3", NULL, 7 },
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{ "pex0", NULL, 8 },
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{ "usb3h0", NULL, 9 },
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{ "usb3h1", NULL, 10 },
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{ "sata0", NULL, 15 },
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{ "sdio", NULL, 17 },
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{ "xor0", NULL, 22 },
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{ "xor1", NULL, 28 },
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{ }
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};
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static void __init armada_39x_clk_gating_init(struct device_node *np)
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{
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mvebu_clk_gating_setup(np, armada_39x_gating_desc);
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}
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CLK_OF_DECLARE(armada_39x_clk_gating, "marvell,armada-390-gating-clock",
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armada_39x_clk_gating_init);
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