626 lines
21 KiB
C
626 lines
21 KiB
C
/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Xiangliang.Yu@amd.com
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*/
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#include "amdgpu.h"
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#include "vi.h"
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#include "bif/bif_5_0_d.h"
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#include "bif/bif_5_0_sh_mask.h"
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#include "vid.h"
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#include "gca/gfx_8_0_d.h"
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#include "gca/gfx_8_0_sh_mask.h"
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#include "gmc_v8_0.h"
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#include "gfx_v8_0.h"
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#include "sdma_v3_0.h"
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#include "tonga_ih.h"
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#include "gmc/gmc_8_2_d.h"
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#include "gmc/gmc_8_2_sh_mask.h"
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#include "oss/oss_3_0_d.h"
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#include "oss/oss_3_0_sh_mask.h"
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#include "gca/gfx_8_0_sh_mask.h"
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#include "dce/dce_10_0_d.h"
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#include "dce/dce_10_0_sh_mask.h"
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#include "smu/smu_7_1_3_d.h"
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#include "mxgpu_vi.h"
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/* VI golden setting */
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static const u32 xgpu_fiji_mgcg_cgcg_init[] = {
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mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
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mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
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mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
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mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
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mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
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mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
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mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
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mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
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mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
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mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
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mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
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mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
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mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
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mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
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mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
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mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
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mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
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mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
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mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
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mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
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mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
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mmPCIE_INDEX, 0xffffffff, 0x0140001c,
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mmPCIE_DATA, 0x000f0000, 0x00000000,
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mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
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mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
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mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
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mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
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mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
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mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
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mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
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mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
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mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
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mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100,
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};
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static const u32 xgpu_fiji_golden_settings_a10[] = {
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mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
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mmDB_DEBUG2, 0xf00fffff, 0x00000400,
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mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
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mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
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mmFBC_MISC, 0x1f311fff, 0x12300000,
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mmHDMI_CONTROL, 0x31000111, 0x00000011,
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mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
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mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
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mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
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mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
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mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
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mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
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mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
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mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
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mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
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mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
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mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
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mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
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mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
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mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
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mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
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mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
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mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
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mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
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mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
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};
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static const u32 xgpu_fiji_golden_common_all[] = {
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mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
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mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
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mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
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mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
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mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
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mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
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mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
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mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
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mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
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mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
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};
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static const u32 xgpu_tonga_mgcg_cgcg_init[] = {
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mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
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mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
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mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
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mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
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mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
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mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
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mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
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mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
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mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
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mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
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mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
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mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
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mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
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mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
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mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
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mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
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mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
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mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
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mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
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mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
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mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
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mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
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mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
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mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
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mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
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mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
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mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
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mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
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mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
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mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
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mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
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mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
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mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
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mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
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mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
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mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
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mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
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mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
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mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
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mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
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mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
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mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
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mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
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mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
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mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
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mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
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mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
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mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
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mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
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mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
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mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
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mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
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mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
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mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
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mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
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mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
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mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
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mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
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mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
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mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
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mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
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mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
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mmPCIE_INDEX, 0xffffffff, 0x0140001c,
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mmPCIE_DATA, 0x000f0000, 0x00000000,
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mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
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mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
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mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
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mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
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mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
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mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
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mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
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mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
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mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
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mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100,
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};
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static const u32 xgpu_tonga_golden_settings_a11[] = {
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mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
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mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
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mmDB_DEBUG2, 0xf00fffff, 0x00000400,
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mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
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mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
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mmFBC_MISC, 0x1f311fff, 0x12300000,
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mmGB_GPU_ID, 0x0000000f, 0x00000000,
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mmHDMI_CONTROL, 0x31000111, 0x00000011,
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mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
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mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
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mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
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mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
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mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
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mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
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mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
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mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
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mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
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mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
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mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
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mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
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mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
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mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
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mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
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mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
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mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
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mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
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mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
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mmTCC_CTRL, 0x00100000, 0xf31fff7f,
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mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
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mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
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mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
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mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
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mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
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mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
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mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
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mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
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mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
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};
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static const u32 xgpu_tonga_golden_common_all[] = {
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mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
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mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
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mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
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mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
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mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
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mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
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mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
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};
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void xgpu_vi_init_golden_registers(struct amdgpu_device *adev)
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{
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switch (adev->asic_type) {
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case CHIP_FIJI:
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amdgpu_device_program_register_sequence(adev,
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xgpu_fiji_mgcg_cgcg_init,
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ARRAY_SIZE(
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xgpu_fiji_mgcg_cgcg_init));
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amdgpu_device_program_register_sequence(adev,
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xgpu_fiji_golden_settings_a10,
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ARRAY_SIZE(
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xgpu_fiji_golden_settings_a10));
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amdgpu_device_program_register_sequence(adev,
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xgpu_fiji_golden_common_all,
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ARRAY_SIZE(
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xgpu_fiji_golden_common_all));
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break;
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case CHIP_TONGA:
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amdgpu_device_program_register_sequence(adev,
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xgpu_tonga_mgcg_cgcg_init,
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ARRAY_SIZE(
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xgpu_tonga_mgcg_cgcg_init));
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amdgpu_device_program_register_sequence(adev,
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xgpu_tonga_golden_settings_a11,
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ARRAY_SIZE(
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xgpu_tonga_golden_settings_a11));
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amdgpu_device_program_register_sequence(adev,
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xgpu_tonga_golden_common_all,
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ARRAY_SIZE(
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xgpu_tonga_golden_common_all));
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break;
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default:
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BUG_ON("Doesn't support chip type.\n");
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break;
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}
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}
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/*
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* Mailbox communication between GPU hypervisor and VFs
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*/
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static void xgpu_vi_mailbox_send_ack(struct amdgpu_device *adev)
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{
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u32 reg;
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int timeout = VI_MAILBOX_TIMEDOUT;
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u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);
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reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
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reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1);
|
|
WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg);
|
|
|
|
/*Wait for RCV_MSG_VALID to be 0*/
|
|
reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
|
|
while (reg & mask) {
|
|
if (timeout <= 0) {
|
|
pr_err("RCV_MSG_VALID is not cleared\n");
|
|
break;
|
|
}
|
|
mdelay(1);
|
|
timeout -=1;
|
|
|
|
reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
|
|
}
|
|
}
|
|
|
|
static void xgpu_vi_mailbox_set_valid(struct amdgpu_device *adev, bool val)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
|
|
reg = REG_SET_FIELD(reg, MAILBOX_CONTROL,
|
|
TRN_MSG_VALID, val ? 1 : 0);
|
|
WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg);
|
|
}
|
|
|
|
static void xgpu_vi_mailbox_trans_msg(struct amdgpu_device *adev,
|
|
enum idh_request req)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0);
|
|
reg = REG_SET_FIELD(reg, MAILBOX_MSGBUF_TRN_DW0,
|
|
MSGBUF_DATA, req);
|
|
WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, reg);
|
|
|
|
xgpu_vi_mailbox_set_valid(adev, true);
|
|
}
|
|
|
|
static int xgpu_vi_mailbox_rcv_msg(struct amdgpu_device *adev,
|
|
enum idh_event event)
|
|
{
|
|
u32 reg;
|
|
u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);
|
|
|
|
/* workaround: host driver doesn't set VALID for CMPL now */
|
|
if (event != IDH_FLR_NOTIFICATION_CMPL) {
|
|
reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
|
|
if (!(reg & mask))
|
|
return -ENOENT;
|
|
}
|
|
|
|
reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0);
|
|
if (reg != event)
|
|
return -ENOENT;
|
|
|
|
/* send ack to PF */
|
|
xgpu_vi_mailbox_send_ack(adev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int xgpu_vi_poll_ack(struct amdgpu_device *adev)
|
|
{
|
|
int r = 0, timeout = VI_MAILBOX_TIMEDOUT;
|
|
u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, TRN_MSG_ACK);
|
|
u32 reg;
|
|
|
|
reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
|
|
while (!(reg & mask)) {
|
|
if (timeout <= 0) {
|
|
pr_err("Doesn't get ack from pf.\n");
|
|
r = -ETIME;
|
|
break;
|
|
}
|
|
mdelay(5);
|
|
timeout -= 5;
|
|
|
|
reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
|
|
}
|
|
|
|
return r;
|
|
}
|
|
|
|
static int xgpu_vi_poll_msg(struct amdgpu_device *adev, enum idh_event event)
|
|
{
|
|
int r = 0, timeout = VI_MAILBOX_TIMEDOUT;
|
|
|
|
r = xgpu_vi_mailbox_rcv_msg(adev, event);
|
|
while (r) {
|
|
if (timeout <= 0) {
|
|
pr_err("Doesn't get ack from pf.\n");
|
|
r = -ETIME;
|
|
break;
|
|
}
|
|
mdelay(5);
|
|
timeout -= 5;
|
|
|
|
r = xgpu_vi_mailbox_rcv_msg(adev, event);
|
|
}
|
|
|
|
return r;
|
|
}
|
|
|
|
static int xgpu_vi_send_access_requests(struct amdgpu_device *adev,
|
|
enum idh_request request)
|
|
{
|
|
int r;
|
|
|
|
xgpu_vi_mailbox_trans_msg(adev, request);
|
|
|
|
/* start to poll ack */
|
|
r = xgpu_vi_poll_ack(adev);
|
|
if (r)
|
|
return r;
|
|
|
|
xgpu_vi_mailbox_set_valid(adev, false);
|
|
|
|
/* start to check msg if request is idh_req_gpu_init_access */
|
|
if (request == IDH_REQ_GPU_INIT_ACCESS ||
|
|
request == IDH_REQ_GPU_FINI_ACCESS ||
|
|
request == IDH_REQ_GPU_RESET_ACCESS) {
|
|
r = xgpu_vi_poll_msg(adev, IDH_READY_TO_ACCESS_GPU);
|
|
if (r) {
|
|
pr_err("Doesn't get ack from pf, give up\n");
|
|
return r;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int xgpu_vi_request_reset(struct amdgpu_device *adev)
|
|
{
|
|
return xgpu_vi_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);
|
|
}
|
|
|
|
static int xgpu_vi_wait_reset_cmpl(struct amdgpu_device *adev)
|
|
{
|
|
return xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL);
|
|
}
|
|
|
|
static int xgpu_vi_request_full_gpu_access(struct amdgpu_device *adev,
|
|
bool init)
|
|
{
|
|
enum idh_request req;
|
|
|
|
req = init ? IDH_REQ_GPU_INIT_ACCESS : IDH_REQ_GPU_FINI_ACCESS;
|
|
return xgpu_vi_send_access_requests(adev, req);
|
|
}
|
|
|
|
static int xgpu_vi_release_full_gpu_access(struct amdgpu_device *adev,
|
|
bool init)
|
|
{
|
|
enum idh_request req;
|
|
int r = 0;
|
|
|
|
req = init ? IDH_REL_GPU_INIT_ACCESS : IDH_REL_GPU_FINI_ACCESS;
|
|
r = xgpu_vi_send_access_requests(adev, req);
|
|
|
|
return r;
|
|
}
|
|
|
|
/* add support mailbox interrupts */
|
|
static int xgpu_vi_mailbox_ack_irq(struct amdgpu_device *adev,
|
|
struct amdgpu_irq_src *source,
|
|
struct amdgpu_iv_entry *entry)
|
|
{
|
|
DRM_DEBUG("get ack intr and do nothing.\n");
|
|
return 0;
|
|
}
|
|
|
|
static int xgpu_vi_set_mailbox_ack_irq(struct amdgpu_device *adev,
|
|
struct amdgpu_irq_src *src,
|
|
unsigned type,
|
|
enum amdgpu_interrupt_state state)
|
|
{
|
|
u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);
|
|
|
|
tmp = REG_SET_FIELD(tmp, MAILBOX_INT_CNTL, ACK_INT_EN,
|
|
(state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0);
|
|
WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void xgpu_vi_mailbox_flr_work(struct work_struct *work)
|
|
{
|
|
struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, flr_work);
|
|
struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);
|
|
|
|
/* wait until RCV_MSG become 3 */
|
|
if (xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL)) {
|
|
pr_err("failed to recieve FLR_CMPL\n");
|
|
return;
|
|
}
|
|
|
|
/* Trigger recovery due to world switch failure */
|
|
amdgpu_device_gpu_recover(adev, NULL, false);
|
|
}
|
|
|
|
static int xgpu_vi_set_mailbox_rcv_irq(struct amdgpu_device *adev,
|
|
struct amdgpu_irq_src *src,
|
|
unsigned type,
|
|
enum amdgpu_interrupt_state state)
|
|
{
|
|
u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);
|
|
|
|
tmp = REG_SET_FIELD(tmp, MAILBOX_INT_CNTL, VALID_INT_EN,
|
|
(state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0);
|
|
WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int xgpu_vi_mailbox_rcv_irq(struct amdgpu_device *adev,
|
|
struct amdgpu_irq_src *source,
|
|
struct amdgpu_iv_entry *entry)
|
|
{
|
|
int r;
|
|
|
|
/* trigger gpu-reset by hypervisor only if TDR disbaled */
|
|
if (!amdgpu_gpu_recovery) {
|
|
/* see what event we get */
|
|
r = xgpu_vi_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION);
|
|
|
|
/* only handle FLR_NOTIFY now */
|
|
if (!r)
|
|
schedule_work(&adev->virt.flr_work);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct amdgpu_irq_src_funcs xgpu_vi_mailbox_ack_irq_funcs = {
|
|
.set = xgpu_vi_set_mailbox_ack_irq,
|
|
.process = xgpu_vi_mailbox_ack_irq,
|
|
};
|
|
|
|
static const struct amdgpu_irq_src_funcs xgpu_vi_mailbox_rcv_irq_funcs = {
|
|
.set = xgpu_vi_set_mailbox_rcv_irq,
|
|
.process = xgpu_vi_mailbox_rcv_irq,
|
|
};
|
|
|
|
void xgpu_vi_mailbox_set_irq_funcs(struct amdgpu_device *adev)
|
|
{
|
|
adev->virt.ack_irq.num_types = 1;
|
|
adev->virt.ack_irq.funcs = &xgpu_vi_mailbox_ack_irq_funcs;
|
|
adev->virt.rcv_irq.num_types = 1;
|
|
adev->virt.rcv_irq.funcs = &xgpu_vi_mailbox_rcv_irq_funcs;
|
|
}
|
|
|
|
int xgpu_vi_mailbox_add_irq_id(struct amdgpu_device *adev)
|
|
{
|
|
int r;
|
|
|
|
r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 135, &adev->virt.rcv_irq);
|
|
if (r)
|
|
return r;
|
|
|
|
r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 138, &adev->virt.ack_irq);
|
|
if (r) {
|
|
amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
|
|
return r;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int xgpu_vi_mailbox_get_irq(struct amdgpu_device *adev)
|
|
{
|
|
int r;
|
|
|
|
r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0);
|
|
if (r)
|
|
return r;
|
|
r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0);
|
|
if (r) {
|
|
amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
|
|
return r;
|
|
}
|
|
|
|
INIT_WORK(&adev->virt.flr_work, xgpu_vi_mailbox_flr_work);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void xgpu_vi_mailbox_put_irq(struct amdgpu_device *adev)
|
|
{
|
|
amdgpu_irq_put(adev, &adev->virt.ack_irq, 0);
|
|
amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
|
|
}
|
|
|
|
const struct amdgpu_virt_ops xgpu_vi_virt_ops = {
|
|
.req_full_gpu = xgpu_vi_request_full_gpu_access,
|
|
.rel_full_gpu = xgpu_vi_release_full_gpu_access,
|
|
.reset_gpu = xgpu_vi_request_reset,
|
|
.wait_reset = xgpu_vi_wait_reset_cmpl,
|
|
.trans_msg = NULL, /* Does not need to trans VF errors to host. */
|
|
};
|