283 lines
7.6 KiB
C
283 lines
7.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MTK_DP__H__
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#define __MTK_DP__H__
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#include "mtk_dp_common.h"
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#define DPTX_CheckSinkCap_TimeOutCnt 0x3
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#define HPD_INT_EVNET BIT(3)
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#define HPD_CONNECT BIT(2)
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#define HPD_DISCONNECT BIT(1)
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#define HPD_INITIAL_STATE 0
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#define DPTX_TBC_SELBUF_CASE 2
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#define DPTX_TBC_BUF_SIZE DPTX_TBC_SELBUF_CASE
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#if (DPTX_TBC_SELBUF_CASE == 2)
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#define DPTX_TBC_BUF_ReadStartAdrThrd 0x08
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#elif (DPTX_TBC_SELBUF_CASE == 1)
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#define DPTX_TBC_BUF_ReadStartAdrThrd 0x10
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#else
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#define DPTX_TBC_BUF_ReadStartAdrThrd 0x1F
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#endif
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#define ENABLE_DPTX_EF_MODE 0x1
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#if (ENABLE_DPTX_EF_MODE == 0x01)
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#define DPTX_AUX_SET_ENAHNCED_FRAME 0x80
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#else
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#define DPTX_AUX_SET_ENAHNCED_FRAME 0x00
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#endif
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#define DPTX_TRAIN_RETRY_LIMIT 0x8
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#define DPTX_TRAIN_MAX_ITERATION 0x5
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enum DPTx_SOURCE_TYPE {
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DPTX_SRC_DPINTF = 0,
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DPTX_SRC_PG = 1,
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};
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enum DPTx_State {
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DPTXSTATE_INITIAL = 0,
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DPTXSTATE_IDLE = 1,
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DPTXSTATE_PREPARE = 2,
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DPTXSTATE_NORMAL = 3,
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};
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enum DPTx_DISP_State {
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DPTX_DISP_NONE = 0,
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DPTX_DISP_RESUME = 1,
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DPTX_DISP_SUSPEND = 2,
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};
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enum DPTx_Return_Status {
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DPTX_NOERR = 0,
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DPTX_PLUG_OUT = 1,
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DPTX_TIMEOUT = 2,
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DPTX_AUTH_FAIL = 3,
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DPTX_EDID_FAIL = 4,
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DPTX_TRANING_FAIL = 5,
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DPTX_RETRANING = 6,
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};
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enum DPTX_TRAINING_STATE {
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DPTX_NTSTATE_STARTUP = 0x0,
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DPTX_NTSTATE_CHECKCAP = 0x1,
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DPTX_NTSTATE_CHECKEDID = 0x2,
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DPTX_NTSTATE_TRAINING_PRE = 0x3,
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DPTX_NTSTATE_TRAINING = 0x4,
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DPTX_NTSTATE_CHECKTIMING = 0x5,
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DPTX_NTSTATE_NORMAL = 0x6,
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DPTX_NTSTATE_POWERSAVE = 0x7,
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DPTX_NTSTATE_DPIDLE = 0x8,
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DPTX_NTSTATE_MAX,
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};
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enum DPTx_FEC_ERROR_COUNT_TYPE {
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FEC_ERROR_COUNT_DISABLE = 0x0,
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FEC_UNCORRECTED_BLOCK_ERROR_COUNT = 0x1,
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FEC_CORRECTED_BLOCK_ERROR_COUNT = 0x2,
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FEC_BIT_ERROR_COUNT = 0x3,
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FEC_PARITY_BLOCK_ERROR_COUNT = 0x4,
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FEC_PARITY_BIT_ERROR_COUNT = 0x5,
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};
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struct DP_CTS_AUTO_REQ {
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unsigned int test_link_training;
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unsigned int test_pattern_req;
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unsigned int test_edid_read;
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unsigned int test_link_rate; //06h:1.62Gbps, 0Ah:2.7Gbps
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unsigned int test_lane_count;
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//01h:color ramps,02h:black&white vertical,03h:color square
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unsigned int test_pattern;
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unsigned int test_h_total;
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unsigned int test_v_total;
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unsigned int test_h_start;
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unsigned int test_v_start;
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unsigned int test_hsync_width;
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unsigned int test_hsync_polarity;
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unsigned int test_vsync_width;
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unsigned int test_vsync_polarity;
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unsigned int test_h_width;
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unsigned int test_v_height;
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unsigned int test_sync_clk;
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unsigned int test_color_fmt;
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unsigned int test_dynamic_range;
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unsigned int test_YCbCr_coefficient;
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unsigned int test_bit_depth;
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unsigned int test_refresh_denominator;
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unsigned int test_interlaced;
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unsigned int test_refresh_rate_numerator;
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unsigned int test_aduio_channel_count;
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unsigned int test_aduio_samling_rate;
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};
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enum DPTx_PG_Sel {
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DPTx_PG_20bit = 0,
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DPTx_PG_80bit = 1,
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DPTx_PG_11bit = 2,
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DPTx_PG_8bit = 3,
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DPTx_PG_PRBS7 = 4,
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};
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enum DP_POWER_STATUS_TYPE {
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DP_POWER_STATUS_NONE = 0,
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DP_POWER_STATUS_AC_ON,
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DP_POWER_STATUS_DC_ON,
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DP_POWER_STATUS_PS_ON,
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DP_POWER_STATUS_DC_OFF,
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DP_POWER_STATUS_POWER_SAVING,
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};
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enum DP_LANECOUNT {
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DP_LANECOUNT_1 = 0x1,
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DP_LANECOUNT_2 = 0x2,
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DP_LANECOUNT_4 = 0x4,
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};
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enum DP_VERSION {
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DP_VERSION_11 = 0x11,
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DP_VERSION_12 = 0x12,
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DP_VERSION_14 = 0x14,
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DP_VERSION_12_14 = 0x16,
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DP_VERSION_14_14 = 0x17,
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DP_VERSION_MAX,
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};
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enum DP_LINKRATE {
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DP_LINKRATE_RBR = 0x6,
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DP_LINKRATE_HBR = 0xA,
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DP_LINKRATE_HBR2 = 0x14,
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DP_LINKRATE_HBR25 = 0x19,
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DP_LINKRATE_HBR3 = 0x1E,
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};
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enum DPTx_SWING_NUM {
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DPTx_SWING0 = 0x00,
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DPTx_SWING1 = 0x01,
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DPTx_SWING2 = 0x02,
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DPTx_SWING3 = 0x03,
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};
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enum DPTx_PREEMPHASIS_NUM {
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DPTx_PREEMPHASIS0 = 0x00,
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DPTx_PREEMPHASIS1 = 0x01,
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DPTx_PREEMPHASIS2 = 0x02,
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DPTx_PREEMPHASIS3 = 0x03,
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};
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//SINK_WIDTH_HIGHT_FPS
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enum DP_VIDEO_TIMING_TYPE {
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SINK_640_480 = 0,
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SINK_800_600 = 1,
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SINK_1280_720 = 2,
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SINK_1280_960 = 3,
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SINK_1280_1024 = 4,
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SINK_1920_1080 = 5,
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SINK_1080_2460 = 6,
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SINK_1920_1200 = 7,
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SINK_1920_1440 = 8,
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SINK_2560_1600 = 9,
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SINK_3840_2160_30 = 10,//4K30
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SINK_3840_2160 = 11,//4k60
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SINK_7680_4320 = 12,
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SINK_MAX,
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};
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enum DP_VIDEO_MUTE {
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video_unmute = 1,
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video_mute = 2,
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};
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enum DPTX_VIDEO_MODE {
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DPTX_VIDEO_INTERLACE = 0,
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DPTX_VIDEO_PROGRESSIVE = 1,
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};
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#define MAX_LANECOUNT DP_LANECOUNT_2
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#define FAKE_DEFAULT_RES 0xFF
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#define DP_VIDEO_TIMING_MASK 0x000000ff
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#define DP_VIDEO_TIMING_SFT 0
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#define DP_COLOR_DEPTH_MASK 0x0000ff00
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#define DP_COLOR_DEPTH_SFT 8
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#define DP_COLOR_FORMAT_MASK 0x00ff0000
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#define DP_COLOR_FORMAT_SFT 16
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#define DP_CHANNEL_2 BIT(0)
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#define DP_CHANNEL_3 BIT(1)
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#define DP_CHANNEL_4 BIT(2)
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#define DP_CHANNEL_5 BIT(3)
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#define DP_CHANNEL_6 BIT(4)
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#define DP_CHANNEL_7 BIT(5)
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#define DP_CHANNEL_8 BIT(6)
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#define DP_SAMPLERATE_32 BIT(0)
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#define DP_SAMPLERATE_44 BIT(1)
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#define DP_SAMPLERATE_48 BIT(2)
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#define DP_SAMPLERATE_96 BIT(3)
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#define DP_SAMPLERATE_192 BIT(4)
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#define DP_BITWIDTH_16 BIT(0)
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#define DP_BITWIDTH_20 BIT(1)
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#define DP_BITWIDTH_24 BIT(2)
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#define DP_CAPABILITY_CHANNEL_MASK 0x7F
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#define DP_CAPABILITY_CHANNEL_SFT 0
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#define DP_CAPABILITY_SAMPLERATE_MASK 0x1F
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#define DP_CAPABILITY_SAMPLERATE_SFT 8
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#define DP_CAPABILITY_BITWIDTH_MASK 0x07
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#define DP_CAPABILITY_BITWIDTH_SFT 16
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void mtk_dp_poweroff(void);
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void mtk_dp_poweron(void);
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void mtk_dp_video_trigger(int res);
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struct edid *mtk_dp_handle_edid(struct mtk_dp *mtk_dp);
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int mdrv_DPTx_SetTrainingStart(struct mtk_dp *mtk_dp);
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void mdrv_DPTx_CheckMaxLinkRate(struct mtk_dp *mtk_dp);
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void mtk_dp_video_config(struct mtk_dp *mtk_dp);
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void mtk_dp_force_res(unsigned int res, unsigned int bpc);
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void mtk_dp_hotplug_uevent(unsigned int status);
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void mtk_dp_enable_4k60(int enable);
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void mdrv_DPTx_FEC_Ready(struct mtk_dp *mtk_dp, u8 err_cnt_sel);
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void mdrv_DPTx_DSC_Support(struct mtk_dp *mtk_dp);
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void mtk_dp_dsc_pps_send(u8 *PPS_128);
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bool mdrv_DPTx_PHY_AutoTest(struct mtk_dp *mtk_dp, u8 ubDPCD_201);
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void mdrv_DPTx_VideoMute(struct mtk_dp *mtk_dp, bool bENABLE);
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void mdrv_DPTx_AudioMute(struct mtk_dp *mtk_dp, bool bENABLE);
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void mdrv_DPTx_SPKG_SDP(struct mtk_dp *mtk_dp, bool bEnable, u8 ucSDPType,
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u8 *pHB, u8 *pDB);
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void mdrv_DPTx_I2S_Audio_Config(struct mtk_dp *mtk_dp);
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void mdrv_DPTx_I2S_Audio_Enable(struct mtk_dp *mtk_dp, bool bEnable);
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void mdrv_DPTx_I2S_Audio_Ch_Status_Set(struct mtk_dp *mtk_dp, u8 ucChannel,
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u8 ucFs, u8 ucWordlength);
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void mdrv_DPTx_I2S_Audio_SDP_Channel_Setting(struct mtk_dp *mtk_dp,
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u8 ucChannel, u8 ucFs, u8 ucWordlength);
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int mdrv_DPTx_HPD_HandleInThread(struct mtk_dp *mtk_dp);
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void mdrv_DPTx_Video_Enable(struct mtk_dp *mtk_dp, bool bEnable);
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DWORD getTimeDiff(DWORD dwPreTime);
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DWORD getSystemTime(void);
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void mtk_dp_fake_plugin(unsigned int status, unsigned int bpc);
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void mtk_dp_force_audio(unsigned int ch, unsigned int fs, unsigned int len);
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void mtk_dp_test(unsigned int status);
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void mtk_dp_fec_enable(unsigned int status);
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void mtk_dp_power_save(unsigned int status);
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void mtk_dp_hdcp_enable(bool enable);
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void mtk_dp_force_hdcp1x(bool enable);
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void mtk_dp_set_adjust_phy(uint8_t index, uint8_t c0, uint8_t cp1);
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int mtk_dp_hdcp_getInfo(char *buffer, int size);
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int mtk_dp_phy_getInfo(char *buffer, int size);
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void mdrv_DPTx_reAuthentication(struct mtk_dp *mtk_dp);
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void mdrv_DPTx_PatternSet(bool enable, int resolution);
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void mdrv_DPTx_set_maxlinkrate(bool enable, int maxlinkrate);
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extern void mhal_DPTx_VideoClock(bool enable, int resolution);
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#endif //__MTK_DP__H__
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