283 lines
6 KiB
C
283 lines
6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __DRTX_TYPE_H__
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#define __DRTX_TYPE_H__
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#include "mtk_drm_ddp_comp.h"
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#include <drm/drm_device.h>
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#include <drm/drm_dp_helper.h>
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#include "drm/mediatek_drm.h"
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#include <drm/drmP.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc_helper.h>
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#include "mtk_dp_hdcp.h"
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#include "mtk_dp_debug.h"
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#ifndef BYTE
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#define BYTE unsigned char
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#endif
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#ifndef WORD
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#define WORD unsigned short
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#endif
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#ifndef DWORD
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#define DWORD unsigned long
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#endif
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#ifndef UINT32
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#define UINT32 unsigned int
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#endif
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#ifndef UINT8
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#define UINT8 unsigned char
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#endif
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#define EDID_SIZE 0x200
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#define ENABLE_DPTX_SSC_FORCEON 0
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#define ENABLE_DPTX_FIX_LRLC 0
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#define ENABLE_DPTX_SSC_OUTPUT 1
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#define ENABLE_DPTX_FIX_TPS2 0
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#define AUX_WRITE_READ_WAIT_TIME 20 //us
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#define DPTX_SUPPORT_DSC 1
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#define DPTX_PHY_LEVEL_COUNT 10
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#define DPTX_PHY_REG_COUNT 6
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#define DPTX_AutoTest_ENABLE 0x1
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#if DPTX_AutoTest_ENABLE
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#define DPTX_TEST_LINK_TRAINING_EN 0x1
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#define DPTX_TEST_PATTERN_EN 0x0
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#define DPTX_TEST_EDID_READ_EN 0x0
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#define DPTX_PHY_TEST_PATTERN_EN 0x1
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#if DPTX_PHY_TEST_PATTERN_EN
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#define DPTX_TEST_D10_2_EN 0x1
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#define DPTX_TEST_SYMBERR_EN 0x0
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#define DPTX_TEST_PRBS7_EN 0x1
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#define DPTX_TEST_PHY80B_EN 0x1
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#define DPTX_TEST_HBR2EYE_EN 0x1
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#define DPTX_TEST_CP2520_P3_EN 0x1
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#else
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#define DPTX_TEST_D10_2_EN 0x0
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#define DPTX_TEST_SYMBERR_EN 0x0
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#define DPTX_TEST_PRBS7_EN 0x0
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#define DPTX_TEST_PHY80B_EN 0x0
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#define DPTX_TEST_HBR2EYE_EN 0x0
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#define DPTX_TEST_CP2520_P3_EN 0x0
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#endif
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#define PATTERN_NONE 0x0
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#define PATTERN_D10_2 0x1
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#define PATTERN_SYMBOL_ERR 0x2
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#define PATTERN_PRBS7 0x3
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#define PATTERN_80B 0x4
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#define PATTERN_HBR2_COM_EYE 0x5
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#define CP2520_PATTERN2 0x6
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#define CP2520_PATTERN3 0x7
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#endif
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enum DP_ATF_CMD {
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DP_ATF_DUMP = 0x20,
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DP_ATF_VIDEO_UNMUTE,
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DP_ATF_CMD_COUNT
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};
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union PPS_T {
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struct{
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BYTE major : 4;
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BYTE minor : 4; //pps0
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BYTE pps_id : 8; //pps1
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BYTE reserved1 : 8; //pps2
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BYTE color_depth : 4;
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BYTE buffer_depth : 4; //pps3
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BYTE reserved2 : 2;
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bool bp_enable : 1;
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bool convert_rgb : 1;
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bool simple_422 : 1;
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bool vbr_enable : 1;
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WORD bit_per_pixel : 10; //pps4-5
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WORD pic_height : 16; //pps6-7
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WORD pic_width : 16; //pps8-9
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WORD slice_height : 16; //pps10-11
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WORD slice_width : 16; //pps12-13
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WORD chunk_size : 16; //pps14-15
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BYTE reserved3 : 6;
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WORD init_xmit_delay : 10; //pps16-17
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WORD init_dec_delay : 16; //pps18-19
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WORD reserved4 : 10;
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BYTE init_scale_val : 6; //pps20-21
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WORD scale_inc_interval : 16;//pps22-23
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BYTE reserved5 : 4;
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WORD scale_dec_interval : 12;//pps24-25
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WORD reserved6 : 11;
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BYTE first_line_offset : 5; //pps26-27
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WORD nfl_bpg_offset : 16; //pps28-29
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WORD slice_bpg_offset : 16; //pps30-31
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WORD init_offset : 16; //pps32-33
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WORD final_offset : 16; //pps34-35
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BYTE reserved7 : 3;
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BYTE min_qp : 5; //pps36
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BYTE reserved8 : 3;
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BYTE max_qp : 5; //pps37
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BYTE rc_param_set[50]; //pps38-87
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BYTE reserved9 : 6;
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bool native_420 : 1;
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bool native_422 : 1; //pps88
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BYTE reserved10 : 3;
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BYTE sec_line_bpg_offset : 5;//pps89
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WORD nsl_bpg_offset : 16; //pps90-91
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WORD sec_line_offset : 16; //pps92-93
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BYTE reserved11[34]; //pps94-127
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} dp_pps;
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BYTE ucPPS[128];
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};
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union MISC_T {
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struct {
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BYTE is_sync_clock : 1;
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BYTE color_format : 2;
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BYTE spec_def1 : 2;
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BYTE color_depth : 3;
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BYTE interlaced : 1;
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BYTE stereo_attr : 2;
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BYTE reserved : 3;
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BYTE is_vsc_sdp : 1;
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BYTE spec_def2 : 1;
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} dp_misc;
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BYTE ucMISC[2];
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};
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struct DPTX_TIMING_PARAMETER {
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WORD Htt;
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WORD Hde;
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WORD Hbk;
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WORD Hfp;
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WORD Hsw;
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bool bHsp;
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WORD Hbp;
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WORD Vtt;
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WORD Vde;
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WORD Vbk;
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WORD Vfp;
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WORD Vsw;
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bool bVsp;
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WORD Vbp;
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BYTE FrameRate;
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DWORD PixRateKhz;
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int Video_ip_mode;
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};
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struct DPTX_TRAINING_INFO {
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bool bSinkEXTCAP_En : 1;
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bool bTPS3 : 1;
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bool bTPS4 : 1;
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bool bSinkSSC_En : 1;
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bool bDPTxAutoTest_EN : 1;
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bool bCablePlugIn : 1;
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bool bCableStateChange : 1;
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bool bDPMstCAP : 1;
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bool bDPMstBranch : 1;
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bool bDWN_STRM_PORT_PRESENT : 1;
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bool cr_done : 1;
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bool eq_done : 1;
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bool set_max_linkrate;
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BYTE ubDPSysVersion;
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BYTE ubSysMaxLinkRate;
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BYTE ubLinkRate;
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BYTE ubLinkLaneCount;
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WORD usPHY_STS;
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BYTE ubDPCD_REV;
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BYTE ubSinkCountNum;
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BYTE ucCheckCapTimes;
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};
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struct DPTX_INFO {
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uint8_t input_src;
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uint8_t depth;
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uint8_t format;
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uint8_t resolution;
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unsigned int audio_caps;
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unsigned int audio_config;
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struct DPTX_TIMING_PARAMETER DPTX_OUTBL;
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bool bPatternGen : 1;
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bool bSinkSSC_En : 1;
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bool bSetAudioMute : 1;
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bool bSetVideoMute : 1;
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bool bAudioMute : 1;
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bool bVideoMute : 1;
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bool bForceHDCP1x : 1;
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#ifdef DPTX_HDCP_ENABLE
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BYTE bAuthStatus;
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struct HDCP1X_INFO hdcp1x_info;
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struct HDCP2_INFO hdcp2_info;
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#endif
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};
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struct DPTX_PHY_PARAMETER {
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unsigned char C0;
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unsigned char CP1;
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};
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struct mtk_dp {
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struct mtk_ddp_comp ddp_comp;
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struct device *dev;
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struct drm_device *drm_dev;
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struct drm_connector conn;
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struct drm_encoder enc;
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int id;
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struct edid *edid;
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struct drm_dp_aux aux;
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u8 rx_cap[16];
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struct drm_display_mode mode;
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struct DPTX_INFO info;
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int state;
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int state_pre;
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struct DPTX_TRAINING_INFO training_info;
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int training_state;
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int training_state_pre;
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wait_queue_head_t control_wq;
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struct task_struct *control_task;
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struct workqueue_struct *dptx_wq;
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struct work_struct hdcp_work;
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struct work_struct dptx_work;
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u32 min_clock;
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u32 max_clock;
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u32 max_hdisplay;
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u32 max_vdisplay;
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void __iomem *regs;
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struct clk *dp_tx_clk;
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bool bUeventToHwc;
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int disp_status; //for DDP
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bool bPowerOn;
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bool audio_enable;
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bool video_enable;
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bool dp_ready;
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bool has_dsc;
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bool has_fec;
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bool dsc_enable;
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struct mtk_drm_private *priv;
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//phy_params[10] = {L0P0,L0P1,L0P2,L0P3,L1P0,L1P1,L1P2,L2P0,L2P1,L3P0};
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struct DPTX_PHY_PARAMETER phy_params[DPTX_PHY_LEVEL_COUNT];
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};
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#endif /*__DRTX_TYPE_H__*/
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