196 lines
5.5 KiB
C
196 lines
5.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Sagy Shih <sagy.shih@mediatek.com>
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*/
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#ifndef __DRAMC_H__
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#define __DRAMC_H__
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/* Feature options */
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/* #define LAST_DRAMC */
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#define SW_ZQCS
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#define SW_TX_TRACKING
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/* #define DVFS_READY */
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#ifdef CONFIG_MTK_EMI
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#define EMI_READY
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#endif
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/* #define RUNTIME_SHMOO */
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#if defined(CONFIG_MTK_ENG_BUILD)
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#define DRAMC_MEMTEST_DEBUG_SUPPORT
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#endif
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/* Registers define */
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#define PDEF_DRAMC0_CHA_REG_0E4 IOMEM((DRAMC_AO_CHA_BASE_ADDR + 0x00e4))
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#define PDEF_DRAMC0_CHA_REG_010 IOMEM((DRAMC_AO_CHA_BASE_ADDR + 0x0010))
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#define PDEF_DRAMC0_CHA_REG_028 IOMEM((DRAMC_AO_CHA_BASE_ADDR + 0x0028))
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#define PDEF_DRAMC0_CHA_REG_0C8 IOMEM((DRAMC_AO_CHA_BASE_ADDR + 0x00c8))
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#define PDEF_DRAMC0_CHA_REG_22C IOMEM((DRAMC_AO_CHA_BASE_ADDR + 0x022C))
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#define PDEF_SPM_AP_SEMAPHORE IOMEM((SLEEP_BASE_ADDR + 0x428))
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#ifdef DVFS_READY
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#define PDEF_SPM_TX_TIMESTAMP IOMEM((SLEEP_BASE_ADDR + 0x618))
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#define PDEF_SYS_TIMER IOMEM((SYS_TIMER_BASE_ADDR + 0x8))
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#endif
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/* Define */
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#define DUAL_FREQ_HIGH 900
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#define DUAL_FREQ_LOW 650
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#define DATA_RATE_THRESHOLD 15
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#define MPLL_CON0_OFFSET 0x280
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#define MPLL_CON1_OFFSET 0x284
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#define MEMPLL5_OFFSET 0x614
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#define DRAMC_ACTIM1 (0x1e8)
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#define TB_DRAM_SPEED
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#define DUAL_FREQ_DIFF_RLWL /* If defined, need to set MR2 in dramcinit.*/
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#define DMA_GDMA_LEN_MAX_MASK (0x000FFFFF)
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#define DMA_GSEC_EN_BIT (0x00000001)
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#define DMA_INT_EN_BIT (0x00000001)
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#define DMA_INT_FLAG_CLR_BIT (0x00000000)
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#define LPDDR3_MODE_REG_2_LOW 0x00140002 /*RL6 WL3.*/
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#define LPDDR2_MODE_REG_2_LOW 0x00040002 /*RL6 WL3.*/
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#define PATTERN1 0x5A5A5A5A
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#define PATTERN2 0xA5A5A5A5
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#define DRAMC_AO_RKCFG (dramc_ao_chx_base+0x034)
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#define DRAMC_AO_PD_CTRL (dramc_ao_chx_base+0x038)
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#define DRAMC_AO_MRS (dramc_ao_chx_base+0x05C)
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#define DRAMC_AO_SPCMD (dramc_ao_chx_base+0x060)
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#define DRAMC_AO_SPCMDCTRL (dramc_ao_chx_base+0x064)
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#define DRAMC_AO_DQSOSCR (dramc_ao_chx_base+0x0C8)
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#define DRAMC_AO_SHUSTATUS (dramc_ao_chx_base+0x0E4)
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#define DRAMC_AO_DQSOSCTHRD (dramc_ao_chx_base+0x854)
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#define DRAMC_AO_CKECTRL (dramc_ao_chx_base+0x024)
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#define DRAMC_AO_DQSOSC_PRD (dramc_ao_chx_base+0x868)
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#define DRAMC_AO_SHU1RK0_PI (dramc_ao_chx_base+0xA0C)
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#define DRAMC_AO_SHU1RK0_DQSOSC (dramc_ao_chx_base+0xA10)
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#define DRAMC_AO_SHU1RK1_PI (dramc_ao_chx_base+0xB0C)
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#define DRAMC_AO_SHU1RK1_DQSOSC (dramc_ao_chx_base+0xB10)
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#define DRAMC_NAO_MISC_STATUSA (dramc_nao_chx_base+0x80)
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#define DRAMC_NAO_SPCMDRESP (dramc_nao_chx_base+0x88)
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#define DRAMC_NAO_MRR_STATUS (dramc_nao_chx_base+0x8C)
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#define DDRPHY_SHU1_R0_B0_DQ7 (ddrphy_chx_base+0xE1C)
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#define DDRPHY_SHU1_R0_B1_DQ7 (ddrphy_chx_base+0xE6C)
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#define DDRPHY_SHU1_R1_B0_DQ7 (ddrphy_chx_base+0xF1C)
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#define DDRPHY_SHU1_R1_B1_DQ7 (ddrphy_chx_base+0xF6C)
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enum TX_RESULT {
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TX_DONE = 0,
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TX_TIMEOUT_MRR_ENABLE,
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TX_TIMEOUT_MRR_DISABLE,
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TX_TIMEOUT_DQSOSC,
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TX_TIMEOUT_DDRPHY,
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TX_FAIL_DATA_RATE,
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TX_FAIL_VARIATION
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};
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extern void __iomem *mt_emi_base_get(void);
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unsigned int mt_dramc_chn_get(unsigned int emi_cona);
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unsigned int mt_dramc_chp_get(unsigned int emi_cona);
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phys_addr_t mt_dramc_rankbase_get(unsigned int rank);
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unsigned int mt_dramc_ta_support_ranks(void);
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#ifdef LAST_DRAMC
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#define LAST_DRAMC_SRAM_MGR
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#define LAST_DRAMC_IP_BASED
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#define LASTDRAMC_KEY 0xD8A3
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#define DBG_INFO_TYPE_MAX 3
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#define DRAMC_STORAGE_API_ERR_OFFSET (28)
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#define STORAGE_READ_API_MASK (0xf)
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#define ERR_PL_UPDATED (0x4)
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phys_addr_t mt_dramc_ta_reserve_addr(unsigned int rank);
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#endif
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#ifdef DRAMC_MEMTEST_DEBUG_SUPPORT
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unsigned int read_dram_mode_reg_by_rank(
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unsigned int mr_index, unsigned int *mr_value,
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unsigned int rank, unsigned int channel);
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#endif
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/* Sysfs config */
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/*We use GPT to measurement how many clk pass in 100us*/
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#ifdef CONFIG_MTK_MEMORY_LOWPOWER
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extern int __init acquire_buffer_from_memory_lowpower(phys_addr_t *addr);
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#else
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static inline int acquire_buffer_from_memory_lowpower(phys_addr_t *addr)
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{
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return -3;
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}
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#endif
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/* DRAMC API config */
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void *mt_dramc_chn_base_get(int channel);
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void *mt_dramc_nao_chn_base_get(int channel);
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void *mt_ddrphy_chn_base_get(int channel);
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void *mt_ddrphy_nao_chn_base_get(int channel);
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/*void get_mempll_table_info(u32 *high_addr, u32 *low_addr, u32 *num);*/
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unsigned int get_dram_data_rate(void);
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unsigned int read_dram_temperature(unsigned char channel);
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/*void sync_hw_gating_value(void);*/
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/*unsigned int is_one_pll_mode(void);*/
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int dram_steps_freq(unsigned int step);
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unsigned int get_shuffle_status(void);
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int get_ddr_type(void);
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unsigned char get_ddr_mr(unsigned int index);
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int get_emi_ch_num(void);
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int dram_can_support_fh(void);
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unsigned int ucDram_Register_Read(unsigned int u4reg_addr);
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unsigned int lpDram_Register_Read(unsigned int Reg_base, unsigned int Offset);
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int enter_pasr_dpd_config(unsigned char segment_rank0,
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unsigned char segment_rank1);
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int exit_pasr_dpd_config(void);
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void del_zqcs_timer(void);
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void add_zqcs_timer(void);
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enum DDRTYPE {
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TYPE_LPDDR3 = 1,
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TYPE_LPDDR4,
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TYPE_LPDDR4X
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};
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enum DRAM_MODE {
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NORMAL_MODE = 0,
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BYTE_MODE,
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R0_NORMAL_R1_BYTE,
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R0_BYTE_R1_NORMAL
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};
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#define PDEF_DRAMC0_CHA_REG_01C IOMEM((DRAMC_AO_CHA_BASE_ADDR + 0x001c))
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enum RANK_MODE {
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RANK_NORMAL = 0,
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RANK_BYTE
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};
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enum {
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DRAM_OK = 0,
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DRAM_FAIL
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}; /* DRAM status type */
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enum {
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DRAMC_NAO_CHA = 0,
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DRAMC_NAO_CHB,
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DRAMC_AO_CHA,
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DRAMC_AO_CHB,
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PHY_NAO_CHA,
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PHY_NAO_CHB,
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PHY_AO_CHA,
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PHY_AO_CHB
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}; /* RegBase */
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enum RANKNUM {
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SINGLE_RANK = 1,
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DUAL_RANK,
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};
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enum {
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CHANNEL_A = 0,
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CHANNEL_B,
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CHANNEL_MAX
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}; /* DRAM_CHANNEL_T */
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#endif /*__WDT_HW_H__*/
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