245 lines
7.3 KiB
C
245 lines
7.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MTK_UART_H__
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#define __MTK_UART_H__
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#include <mt-plat/sync_write.h>
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#include "platform_uart.h"
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/*---------------------------------------------------------------------------*/
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#if defined(ENABLE_VFIFO_DEBUG)
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/*---------------------------------------------------------------------------*/
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#define DGBUF_INIT(v) \
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do { \
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if (UART_DEBUG_EVT(DBG_EVT_BUF)) { \
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v->dbgidx = (v->dbgidx+1)%(ARRAY_SIZE(v->dbg)); \
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v->cur = &v->dbg[v->dbgidx]; \
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v->cur->idx = 0; \
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} \
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} while (0)
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/*---------------------------------------------------------------------------*/
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#define DGBUF_PUSH_CH(v, c) \
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do { \
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if (UART_DEBUG_EVT(DBG_EVT_BUF)) \
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v->cur->dat[v->cur->idx++] = (char)(c); \
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} while (0)
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/*---------------------------------------------------------------------------*/
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#define DGBUF_PUSH_STR(v, s, l) \
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do { \
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if (UART_DEBUG_EVT(DBG_EVT_BUF)) {\
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memcpy(&v->cur->dat[v->cur->idx], (s), (l)); \
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v->cur->idx += (l); \
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} \
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} while (0)
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#else
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/*---------------------------------------------------------------------------*/
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#define DGBUF_INIT(v)
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#define DGBUF_PUSH_CH(v, c)
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#define DGBUF_PUSH_STR(v, s, l)
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#endif
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/******************************************************************************
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* ENUM & STRUCT
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*****************************************************************************
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*/
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enum {
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UART_NON_DMA,
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UART_TX_DMA,
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UART_TX_VFIFO_DMA,
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UART_RX_VFIFO_DMA,
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};
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/*---------------------------------------------------------------------------*/
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enum {
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UART_TX_VFIFO,
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UART_RX_VFIFO,
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UART_VFIFO_NUM
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};
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/*---------------------------------------------------------------------------*/
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/* uart dma mode */
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enum {
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UART_DMA_MODE_0,
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UART_DMA_MODE_1,
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};
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/*---------------------------------------------------------------------------*/
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/* flow control mode */
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enum {
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UART_FC_NONE, /*NO flow control */
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UART_FC_SW,/*MTK SW Flow Control, differs from Linux Flow Control */
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UART_FC_HW, /*HW Flow Control */
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};
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/*---------------------------------------------------------------------------*/
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struct mtk_uart_setting {
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u8 tx_mode;
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u8 rx_mode;
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u8 dma_mode;
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u8 sysrq;
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int tx_trig;
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int rx_trig;
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unsigned long uart_base;
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unsigned long uart_phys_base;
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unsigned long irq_flags;
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#if !defined(CONFIG_MTK_LEGACY)
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struct clk *clk_uart_main;
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#endif /* !defined(CONFIG_MTK_LEGACY) */
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u8 irq_num;
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u8 irq_sen;
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u8 set_bit; /*APMCU_CG_SET0 */
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u8 clr_bit; /*APMCU_CG_CLR0 */
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int pll_id;
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u8 hw_flow; /*support hardware flow control or not?! */
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u8 vff; /*support vfifo or not!? */
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u16 _align;
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bool support_33bits;
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};
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/*---------------------------------------------------------------------------*/
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#define C_UART_DEBUG_BUF_NUM (5)
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/*---------------------------------------------------------------------------*/
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struct mtk_uart_buf {
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unsigned char *dat;
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unsigned int idx;
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unsigned int len;
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};
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/*---------------------------------------------------------------------------*/
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struct mtk_uart_vfifo {
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struct mtk_uart_dma *dma; /* vfifo dma owner */
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/*configuration */
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u16 ch;
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u16 size;
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u16 trig;
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u16 type; /*UART_RX_VFIFO / UART_TX_VFIFO */
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void *base;
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void *port; /*only tx */
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void *addr;
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atomic_t reg_cb;
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atomic_t entry; /* entry count */
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spinlock_t iolock;
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struct timer_list timer; /* vfifo timer */
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struct hrtimer flush;
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dma_addr_t dmahd; /* dma handle */
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struct tasklet_struct flush_tasklet;
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struct mtk_uart_buf dbg[C_UART_DEBUG_BUF_NUM];
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struct mtk_uart_buf *cur;
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int dbgidx;
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unsigned int irq_id;
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};
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/*---------------------------------------------------------------------------*/
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struct mtk_uart_dma {
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struct mtk_uart *uart; /* dma uart */
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atomic_t free; /* dma channel free */
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unsigned short mode; /* dma mode */
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unsigned short dir; /* dma transfer direction */
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struct tasklet_struct tasklet; /* dma handling tasklet */
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struct completion done; /* dma transfer done */
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struct mtk_uart_vfifo *vfifo; /* dma vfifo */
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};
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/*---------------------------------------------------------------------------*/
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struct mtk_uart_register {
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unsigned int dll;
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unsigned int dlh;
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unsigned int ier;
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unsigned int lcr;
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unsigned int mcr;
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unsigned int fcr;
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unsigned int lsr;
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unsigned int efr;
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unsigned int highspeed;
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unsigned int sample_count;
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unsigned int sample_point;
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unsigned int fracdiv_l;
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unsigned int fracdiv_m;
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unsigned int escape_en;
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unsigned int guard;
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unsigned int rx_sel;
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};
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/*---------------------------------------------------------------------------*/
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struct mtk_uart {
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struct uart_port port;
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unsigned long base;
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int nport;
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unsigned int old_status;
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unsigned int tx_stop;
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unsigned int rx_stop;
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unsigned int ms_enable;
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unsigned int auto_baud;
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unsigned int line_status;
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unsigned int ignore_rx;
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unsigned int flow_ctrl;
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unsigned long pending_tx_reqs;
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unsigned long tx_trig; /* tx fifo trigger level */
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unsigned long rx_trig; /* rx fifo trigger level */
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unsigned long sysclk;
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unsigned long evt_mask;
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unsigned long lsr_status;
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int baudrate; /*current baudrate */
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int custom_baud; /*custom baudrate passed from serial_struct */
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int dma_mode;
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int tx_mode;
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int rx_mode;
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int fctl_mode; /*flow control */
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int poweron_count;
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int timeout_count; /*for console write */
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/* FCR register is a write only register */
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unsigned int fcr_back_up;
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struct mtk_uart_register registers;
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struct mtk_uart_dma dma_tx;
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struct mtk_uart_dma dma_rx;
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struct mtk_uart_vfifo *tx_vfifo;
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struct mtk_uart_vfifo *rx_vfifo;
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struct mtk_uart_setting *setting;
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unsigned int (*write_allow)(struct mtk_uart *uart);
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unsigned int (*read_allow)(struct mtk_uart *uart);
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void (*write_byte)(struct mtk_uart *uart, unsigned int byte);
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unsigned int (*read_byte)(struct mtk_uart *uart);
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unsigned int (*read_status)(struct mtk_uart *uart);
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};
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/*---------------------------------------------------------------------------*/
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/* fiq debugger */
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/*---------------------------------------------------------------------------*/
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struct fiq_dbg_event {
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u32 iir;
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int data;
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};
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/*---------------------------------------------------------------------------*/
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/* #define UART_READ8(REG) __raw_readb(REG) */
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/* #define UART_READ16(REG) __raw_readw(REG) */
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/* #define UART_READ32(REG) __raw_readl(REG) */
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#define UART_READ8(REG) (*(unsigned char *)(REG))
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#define UART_READ16(REG) (*(unsigned short *)(REG))
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#define UART_READ32(REG) (*(unsigned int *)(REG))
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#define reg_sync_writeb(v, a) mt_reg_sync_writeb(v, a)
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#define reg_sync_writel(v, a) mt_reg_sync_writel(v, a)
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/*---------------------------------------------------------------------------*/
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#define UART_SET_BITS(BS, REG) ((*(u32 *)(REG)) |= (u32)(BS))
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#define UART_CLR_BITS(BS, REG) ((*(u32 *)(REG)) &= ~((u32)(BS)))
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/*---------------------------------------------------------------------------*/
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extern spinlock_t mtk_console_lock;
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extern struct mtk_uart *console_port;
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unsigned int mtk_uart_pdn_enable(char *port, int enable);
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extern void update_history_byte(char is_tx, int nport, unsigned char byte);
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extern void update_history_time(char is_tx, int nport);
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extern void update_history_bulk(char is_tx, int nport,
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unsigned char *chars, int count);
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extern struct mtk_uart mtk_uarts[UART_NR];
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#ifdef CONFIG_FIQ_DEBUGGER
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extern struct resource fiq_resource[];
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#endif /* CONFIG_FIQ_DEBUGGER */
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#endif /* MTK_UART_H */
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