459 lines
12 KiB
C
459 lines
12 KiB
C
/*
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* Copyright (C) 2016-2017 Netronome Systems, Inc.
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*
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* This software is dual licensed under the GNU General License Version 2,
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* June 1991 as shown in the file COPYING in the top-level directory of this
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* source tree or the BSD 2-Clause License provided below. You have the
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* option to license this software under the complete terms of either license.
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*
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* The BSD 2-Clause License:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* 1. Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __NFP_ASM_H__
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#define __NFP_ASM_H__ 1
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#include <linux/bitfield.h>
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#include <linux/bug.h>
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#include <linux/types.h>
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#define REG_NONE 0
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#define REG_WIDTH 4
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#define RE_REG_NO_DST 0x020
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#define RE_REG_IMM 0x020
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#define RE_REG_IMM_encode(x) \
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(RE_REG_IMM | ((x) & 0x1f) | (((x) & 0x60) << 1))
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#define RE_REG_IMM_MAX 0x07fULL
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#define RE_REG_LM 0x050
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#define RE_REG_LM_IDX 0x008
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#define RE_REG_LM_IDX_MAX 0x7
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#define RE_REG_XFR 0x080
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#define UR_REG_XFR 0x180
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#define UR_REG_LM 0x200
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#define UR_REG_LM_IDX 0x020
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#define UR_REG_LM_POST_MOD 0x010
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#define UR_REG_LM_POST_MOD_DEC 0x001
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#define UR_REG_LM_IDX_MAX 0xf
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#define UR_REG_NN 0x280
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#define UR_REG_NO_DST 0x300
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#define UR_REG_IMM UR_REG_NO_DST
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#define UR_REG_IMM_encode(x) (UR_REG_IMM | (x))
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#define UR_REG_IMM_MAX 0x0ffULL
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#define OP_BR_BASE 0x0d800000020ULL
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#define OP_BR_BASE_MASK 0x0f8000c3ce0ULL
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#define OP_BR_MASK 0x0000000001fULL
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#define OP_BR_EV_PIP 0x00000000300ULL
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#define OP_BR_CSS 0x0000003c000ULL
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#define OP_BR_DEFBR 0x00000300000ULL
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#define OP_BR_ADDR_LO 0x007ffc00000ULL
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#define OP_BR_ADDR_HI 0x10000000000ULL
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#define OP_BR_BIT_BASE 0x0d000000000ULL
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#define OP_BR_BIT_BASE_MASK 0x0f800080300ULL
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#define OP_BR_BIT_A_SRC 0x000000000ffULL
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#define OP_BR_BIT_B_SRC 0x0000003fc00ULL
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#define OP_BR_BIT_BV 0x00000040000ULL
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#define OP_BR_BIT_SRC_LMEXTN 0x40000000000ULL
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#define OP_BR_BIT_DEFBR OP_BR_DEFBR
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#define OP_BR_BIT_ADDR_LO OP_BR_ADDR_LO
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#define OP_BR_BIT_ADDR_HI OP_BR_ADDR_HI
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static inline bool nfp_is_br(u64 insn)
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{
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return (insn & OP_BR_BASE_MASK) == OP_BR_BASE ||
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(insn & OP_BR_BIT_BASE_MASK) == OP_BR_BIT_BASE;
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}
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enum br_mask {
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BR_BEQ = 0x00,
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BR_BNE = 0x01,
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BR_BMI = 0x02,
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BR_BHS = 0x04,
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BR_BCC = 0x05,
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BR_BLO = 0x05,
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BR_BGE = 0x08,
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BR_BLT = 0x09,
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BR_UNC = 0x18,
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};
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enum br_ev_pip {
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BR_EV_PIP_UNCOND = 0,
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BR_EV_PIP_COND = 1,
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};
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enum br_ctx_signal_state {
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BR_CSS_NONE = 2,
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};
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u16 br_get_offset(u64 instr);
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void br_set_offset(u64 *instr, u16 offset);
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void br_add_offset(u64 *instr, u16 offset);
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#define OP_BBYTE_BASE 0x0c800000000ULL
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#define OP_BB_A_SRC 0x000000000ffULL
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#define OP_BB_BYTE 0x00000000300ULL
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#define OP_BB_B_SRC 0x0000003fc00ULL
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#define OP_BB_I8 0x00000040000ULL
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#define OP_BB_EQ 0x00000080000ULL
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#define OP_BB_DEFBR 0x00000300000ULL
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#define OP_BB_ADDR_LO 0x007ffc00000ULL
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#define OP_BB_ADDR_HI 0x10000000000ULL
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#define OP_BB_SRC_LMEXTN 0x40000000000ULL
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#define OP_BALU_BASE 0x0e800000000ULL
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#define OP_BA_A_SRC 0x000000003ffULL
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#define OP_BA_B_SRC 0x000000ffc00ULL
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#define OP_BA_DEFBR 0x00000300000ULL
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#define OP_BA_ADDR_HI 0x0007fc00000ULL
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#define OP_IMMED_A_SRC 0x000000003ffULL
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#define OP_IMMED_B_SRC 0x000000ffc00ULL
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#define OP_IMMED_IMM 0x0000ff00000ULL
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#define OP_IMMED_WIDTH 0x00060000000ULL
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#define OP_IMMED_INV 0x00080000000ULL
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#define OP_IMMED_SHIFT 0x00600000000ULL
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#define OP_IMMED_BASE 0x0f000000000ULL
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#define OP_IMMED_WR_AB 0x20000000000ULL
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#define OP_IMMED_SRC_LMEXTN 0x40000000000ULL
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#define OP_IMMED_DST_LMEXTN 0x80000000000ULL
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enum immed_width {
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IMMED_WIDTH_ALL = 0,
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IMMED_WIDTH_BYTE = 1,
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IMMED_WIDTH_WORD = 2,
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};
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enum immed_shift {
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IMMED_SHIFT_0B = 0,
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IMMED_SHIFT_1B = 1,
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IMMED_SHIFT_2B = 2,
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};
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u16 immed_get_value(u64 instr);
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void immed_set_value(u64 *instr, u16 immed);
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void immed_add_value(u64 *instr, u16 offset);
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#define OP_SHF_BASE 0x08000000000ULL
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#define OP_SHF_A_SRC 0x000000000ffULL
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#define OP_SHF_SC 0x00000000300ULL
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#define OP_SHF_B_SRC 0x0000003fc00ULL
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#define OP_SHF_I8 0x00000040000ULL
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#define OP_SHF_SW 0x00000080000ULL
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#define OP_SHF_DST 0x0000ff00000ULL
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#define OP_SHF_SHIFT 0x001f0000000ULL
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#define OP_SHF_OP 0x00e00000000ULL
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#define OP_SHF_DST_AB 0x01000000000ULL
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#define OP_SHF_WR_AB 0x20000000000ULL
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#define OP_SHF_SRC_LMEXTN 0x40000000000ULL
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#define OP_SHF_DST_LMEXTN 0x80000000000ULL
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enum shf_op {
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SHF_OP_NONE = 0,
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SHF_OP_AND = 2,
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SHF_OP_OR = 5,
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SHF_OP_ASHR = 6,
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};
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enum shf_sc {
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SHF_SC_R_ROT = 0,
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SHF_SC_NONE = SHF_SC_R_ROT,
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SHF_SC_R_SHF = 1,
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SHF_SC_L_SHF = 2,
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SHF_SC_R_DSHF = 3,
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};
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#define OP_ALU_A_SRC 0x000000003ffULL
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#define OP_ALU_B_SRC 0x000000ffc00ULL
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#define OP_ALU_DST 0x0003ff00000ULL
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#define OP_ALU_SW 0x00040000000ULL
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#define OP_ALU_OP 0x00f80000000ULL
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#define OP_ALU_DST_AB 0x01000000000ULL
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#define OP_ALU_BASE 0x0a000000000ULL
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#define OP_ALU_WR_AB 0x20000000000ULL
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#define OP_ALU_SRC_LMEXTN 0x40000000000ULL
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#define OP_ALU_DST_LMEXTN 0x80000000000ULL
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enum alu_op {
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ALU_OP_NONE = 0x00,
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ALU_OP_ADD = 0x01,
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ALU_OP_NOT = 0x04,
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ALU_OP_ADD_2B = 0x05,
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ALU_OP_AND = 0x08,
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ALU_OP_AND_NOT_A = 0x0c,
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ALU_OP_SUB_C = 0x0d,
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ALU_OP_AND_NOT_B = 0x10,
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ALU_OP_ADD_C = 0x11,
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ALU_OP_OR = 0x14,
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ALU_OP_SUB = 0x15,
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ALU_OP_XOR = 0x18,
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};
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enum alu_dst_ab {
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ALU_DST_A = 0,
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ALU_DST_B = 1,
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};
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#define OP_LDF_BASE 0x0c000000000ULL
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#define OP_LDF_A_SRC 0x000000000ffULL
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#define OP_LDF_SC 0x00000000300ULL
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#define OP_LDF_B_SRC 0x0000003fc00ULL
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#define OP_LDF_I8 0x00000040000ULL
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#define OP_LDF_SW 0x00000080000ULL
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#define OP_LDF_ZF 0x00000100000ULL
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#define OP_LDF_BMASK 0x0000f000000ULL
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#define OP_LDF_SHF 0x001f0000000ULL
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#define OP_LDF_WR_AB 0x20000000000ULL
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#define OP_LDF_SRC_LMEXTN 0x40000000000ULL
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#define OP_LDF_DST_LMEXTN 0x80000000000ULL
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#define OP_CMD_A_SRC 0x000000000ffULL
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#define OP_CMD_CTX 0x00000000300ULL
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#define OP_CMD_B_SRC 0x0000003fc00ULL
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#define OP_CMD_TOKEN 0x000000c0000ULL
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#define OP_CMD_XFER 0x00001f00000ULL
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#define OP_CMD_CNT 0x0000e000000ULL
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#define OP_CMD_SIG 0x000f0000000ULL
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#define OP_CMD_TGT_CMD 0x07f00000000ULL
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#define OP_CMD_INDIR 0x20000000000ULL
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#define OP_CMD_MODE 0x1c0000000000ULL
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struct cmd_tgt_act {
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u8 token;
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u8 tgt_cmd;
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};
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enum cmd_tgt_map {
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CMD_TGT_READ8,
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CMD_TGT_WRITE8_SWAP,
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CMD_TGT_WRITE32_SWAP,
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CMD_TGT_READ32,
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CMD_TGT_READ32_LE,
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CMD_TGT_READ32_SWAP,
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CMD_TGT_READ_LE,
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CMD_TGT_READ_SWAP_LE,
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CMD_TGT_ADD,
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CMD_TGT_ADD_IMM,
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__CMD_TGT_MAP_SIZE,
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};
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extern const struct cmd_tgt_act cmd_tgt_act[__CMD_TGT_MAP_SIZE];
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enum cmd_mode {
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CMD_MODE_40b_AB = 0,
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CMD_MODE_40b_BA = 1,
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CMD_MODE_32b = 4,
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};
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enum cmd_ctx_swap {
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CMD_CTX_SWAP = 0,
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CMD_CTX_SWAP_DEFER1 = 1,
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CMD_CTX_SWAP_DEFER2 = 2,
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CMD_CTX_NO_SWAP = 3,
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};
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#define CMD_OVE_DATA GENMASK(5, 3)
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#define CMD_OVE_LEN BIT(7)
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#define CMD_OV_LEN GENMASK(12, 8)
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#define OP_LCSR_BASE 0x0fc00000000ULL
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#define OP_LCSR_A_SRC 0x000000003ffULL
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#define OP_LCSR_B_SRC 0x000000ffc00ULL
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#define OP_LCSR_WRITE 0x00000200000ULL
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#define OP_LCSR_ADDR 0x001ffc00000ULL
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#define OP_LCSR_SRC_LMEXTN 0x40000000000ULL
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#define OP_LCSR_DST_LMEXTN 0x80000000000ULL
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enum lcsr_wr_src {
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LCSR_WR_AREG,
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LCSR_WR_BREG,
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LCSR_WR_IMM,
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};
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#define OP_CARB_BASE 0x0e000000000ULL
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#define OP_CARB_OR 0x00000010000ULL
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#define NFP_CSR_CTX_PTR 0x20
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#define NFP_CSR_ACT_LM_ADDR0 0x64
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#define NFP_CSR_ACT_LM_ADDR1 0x6c
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#define NFP_CSR_ACT_LM_ADDR2 0x94
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#define NFP_CSR_ACT_LM_ADDR3 0x9c
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#define NFP_CSR_PSEUDO_RND_NUM 0x148
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/* Software register representation, independent of operand type */
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#define NN_REG_TYPE GENMASK(31, 24)
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#define NN_REG_LM_IDX GENMASK(23, 22)
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#define NN_REG_LM_IDX_HI BIT(23)
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#define NN_REG_LM_IDX_LO BIT(22)
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#define NN_REG_LM_MOD GENMASK(21, 20)
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#define NN_REG_VAL GENMASK(7, 0)
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enum nfp_bpf_reg_type {
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NN_REG_GPR_A = BIT(0),
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NN_REG_GPR_B = BIT(1),
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NN_REG_GPR_BOTH = NN_REG_GPR_A | NN_REG_GPR_B,
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NN_REG_NNR = BIT(2),
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NN_REG_XFER = BIT(3),
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NN_REG_IMM = BIT(4),
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NN_REG_NONE = BIT(5),
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NN_REG_LMEM = BIT(6),
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};
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enum nfp_bpf_lm_mode {
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NN_LM_MOD_NONE = 0,
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NN_LM_MOD_INC,
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NN_LM_MOD_DEC,
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};
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#define reg_both(x) __enc_swreg((x), NN_REG_GPR_BOTH)
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#define reg_a(x) __enc_swreg((x), NN_REG_GPR_A)
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#define reg_b(x) __enc_swreg((x), NN_REG_GPR_B)
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#define reg_nnr(x) __enc_swreg((x), NN_REG_NNR)
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#define reg_xfer(x) __enc_swreg((x), NN_REG_XFER)
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#define reg_imm(x) __enc_swreg((x), NN_REG_IMM)
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#define reg_none() __enc_swreg(0, NN_REG_NONE)
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#define reg_lm(x, off) __enc_swreg_lm((x), NN_LM_MOD_NONE, (off))
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#define reg_lm_inc(x) __enc_swreg_lm((x), NN_LM_MOD_INC, 0)
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#define reg_lm_dec(x) __enc_swreg_lm((x), NN_LM_MOD_DEC, 0)
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#define __reg_lm(x, mod, off) __enc_swreg_lm((x), (mod), (off))
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typedef __u32 __bitwise swreg;
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static inline swreg __enc_swreg(u16 id, u8 type)
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{
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return (__force swreg)(id | FIELD_PREP(NN_REG_TYPE, type));
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}
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static inline swreg __enc_swreg_lm(u8 id, enum nfp_bpf_lm_mode mode, u8 off)
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{
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WARN_ON(id > 3 || (off && mode != NN_LM_MOD_NONE));
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return (__force swreg)(FIELD_PREP(NN_REG_TYPE, NN_REG_LMEM) |
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FIELD_PREP(NN_REG_LM_IDX, id) |
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FIELD_PREP(NN_REG_LM_MOD, mode) |
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off);
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}
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static inline u32 swreg_raw(swreg reg)
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{
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return (__force u32)reg;
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}
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static inline enum nfp_bpf_reg_type swreg_type(swreg reg)
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{
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return FIELD_GET(NN_REG_TYPE, swreg_raw(reg));
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}
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static inline u16 swreg_value(swreg reg)
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{
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return FIELD_GET(NN_REG_VAL, swreg_raw(reg));
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}
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static inline bool swreg_lm_idx(swreg reg)
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{
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return FIELD_GET(NN_REG_LM_IDX_LO, swreg_raw(reg));
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}
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static inline bool swreg_lmextn(swreg reg)
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{
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return FIELD_GET(NN_REG_LM_IDX_HI, swreg_raw(reg));
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}
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static inline enum nfp_bpf_lm_mode swreg_lm_mode(swreg reg)
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{
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return FIELD_GET(NN_REG_LM_MOD, swreg_raw(reg));
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}
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struct nfp_insn_ur_regs {
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enum alu_dst_ab dst_ab;
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u16 dst;
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u16 areg, breg;
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bool swap;
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bool wr_both;
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bool dst_lmextn;
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bool src_lmextn;
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};
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struct nfp_insn_re_regs {
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enum alu_dst_ab dst_ab;
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u8 dst;
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u8 areg, breg;
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bool swap;
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bool wr_both;
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bool i8;
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bool dst_lmextn;
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bool src_lmextn;
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};
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int swreg_to_unrestricted(swreg dst, swreg lreg, swreg rreg,
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struct nfp_insn_ur_regs *reg);
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int swreg_to_restricted(swreg dst, swreg lreg, swreg rreg,
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struct nfp_insn_re_regs *reg, bool has_imm8);
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#define NFP_USTORE_PREFETCH_WINDOW 8
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int nfp_ustore_check_valid_no_ecc(u64 insn);
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u64 nfp_ustore_calc_ecc_insn(u64 insn);
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#define NFP_IND_ME_REFL_WR_SIG_INIT 3
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#define NFP_IND_ME_CTX_PTR_BASE_MASK GENMASK(9, 0)
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#define NFP_IND_NUM_CONTEXTS 8
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static inline u32 nfp_get_ind_csr_ctx_ptr_offs(u32 read_offset)
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{
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return (read_offset & ~NFP_IND_ME_CTX_PTR_BASE_MASK) | NFP_CSR_CTX_PTR;
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}
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enum mul_type {
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MUL_TYPE_START = 0x00,
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MUL_TYPE_STEP_24x8 = 0x01,
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MUL_TYPE_STEP_16x16 = 0x02,
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MUL_TYPE_STEP_32x32 = 0x03,
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};
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enum mul_step {
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MUL_STEP_1 = 0x00,
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MUL_STEP_NONE = MUL_STEP_1,
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MUL_STEP_2 = 0x01,
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MUL_STEP_3 = 0x02,
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MUL_STEP_4 = 0x03,
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MUL_LAST = 0x04,
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MUL_LAST_2 = 0x05,
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};
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#define OP_MUL_BASE 0x0f800000000ULL
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#define OP_MUL_A_SRC 0x000000003ffULL
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#define OP_MUL_B_SRC 0x000000ffc00ULL
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#define OP_MUL_STEP 0x00000700000ULL
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#define OP_MUL_DST_AB 0x00000800000ULL
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#define OP_MUL_SW 0x00040000000ULL
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#define OP_MUL_TYPE 0x00180000000ULL
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#define OP_MUL_WR_AB 0x20000000000ULL
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#define OP_MUL_SRC_LMEXTN 0x40000000000ULL
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#define OP_MUL_DST_LMEXTN 0x80000000000ULL
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#endif
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