614 lines
15 KiB
C
614 lines
15 KiB
C
/*
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* Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef __MT76_H
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#define __MT76_H
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <linux/skbuff.h>
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#include <linux/leds.h>
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#include <linux/usb.h>
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#include <net/mac80211.h>
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#include "util.h"
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#define MT_TX_RING_SIZE 256
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#define MT_MCU_RING_SIZE 32
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#define MT_RX_BUF_SIZE 2048
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struct mt76_dev;
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struct mt76_wcid;
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struct mt76_bus_ops {
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u32 (*rr)(struct mt76_dev *dev, u32 offset);
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void (*wr)(struct mt76_dev *dev, u32 offset, u32 val);
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u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val);
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void (*copy)(struct mt76_dev *dev, u32 offset, const void *data,
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int len);
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};
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enum mt76_txq_id {
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MT_TXQ_VO = IEEE80211_AC_VO,
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MT_TXQ_VI = IEEE80211_AC_VI,
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MT_TXQ_BE = IEEE80211_AC_BE,
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MT_TXQ_BK = IEEE80211_AC_BK,
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MT_TXQ_PSD,
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MT_TXQ_MCU,
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MT_TXQ_BEACON,
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MT_TXQ_CAB,
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__MT_TXQ_MAX
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};
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enum mt76_rxq_id {
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MT_RXQ_MAIN,
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MT_RXQ_MCU,
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__MT_RXQ_MAX
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};
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struct mt76_queue_buf {
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dma_addr_t addr;
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int len;
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};
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struct mt76u_buf {
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struct mt76_dev *dev;
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struct urb *urb;
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size_t len;
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bool done;
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};
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struct mt76_queue_entry {
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union {
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void *buf;
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struct sk_buff *skb;
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};
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union {
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struct mt76_txwi_cache *txwi;
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struct mt76u_buf ubuf;
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};
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bool schedule;
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};
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struct mt76_queue_regs {
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u32 desc_base;
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u32 ring_size;
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u32 cpu_idx;
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u32 dma_idx;
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} __packed __aligned(4);
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struct mt76_queue {
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struct mt76_queue_regs __iomem *regs;
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spinlock_t lock;
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struct mt76_queue_entry *entry;
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struct mt76_desc *desc;
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struct list_head swq;
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int swq_queued;
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u16 first;
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u16 head;
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u16 tail;
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int ndesc;
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int queued;
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int buf_size;
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u8 buf_offset;
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u8 hw_idx;
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dma_addr_t desc_dma;
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struct sk_buff *rx_head;
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};
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struct mt76_queue_ops {
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int (*init)(struct mt76_dev *dev);
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int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q);
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int (*add_buf)(struct mt76_dev *dev, struct mt76_queue *q,
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struct mt76_queue_buf *buf, int nbufs, u32 info,
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struct sk_buff *skb, void *txwi);
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int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q,
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struct sk_buff *skb, struct mt76_wcid *wcid,
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struct ieee80211_sta *sta);
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void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
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int *len, u32 *info, bool *more);
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void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid);
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void (*tx_cleanup)(struct mt76_dev *dev, enum mt76_txq_id qid,
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bool flush);
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void (*kick)(struct mt76_dev *dev, struct mt76_queue *q);
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};
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enum mt76_wcid_flags {
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MT_WCID_FLAG_CHECK_PS,
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MT_WCID_FLAG_PS,
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};
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struct mt76_wcid {
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struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS];
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struct work_struct aggr_work;
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unsigned long flags;
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u8 idx;
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u8 hw_key_idx;
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u8 sta:1;
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u8 rx_check_pn;
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u8 rx_key_pn[IEEE80211_NUM_TIDS][6];
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__le16 tx_rate;
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bool tx_rate_set;
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u8 tx_rate_nss;
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s8 max_txpwr_adj;
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bool sw_iv;
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};
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struct mt76_txq {
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struct list_head list;
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struct mt76_queue *hwq;
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struct mt76_wcid *wcid;
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struct sk_buff_head retry_q;
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u16 agg_ssn;
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bool send_bar;
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bool aggr;
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};
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struct mt76_txwi_cache {
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u32 txwi[8];
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dma_addr_t dma_addr;
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struct list_head list;
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};
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struct mt76_rx_tid {
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struct rcu_head rcu_head;
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struct mt76_dev *dev;
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spinlock_t lock;
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struct delayed_work reorder_work;
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u16 head;
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u16 size;
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u16 nframes;
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u8 started:1, stopped:1, timer_pending:1;
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struct sk_buff *reorder_buf[];
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};
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enum {
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MT76_STATE_INITIALIZED,
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MT76_STATE_RUNNING,
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MT76_STATE_MCU_RUNNING,
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MT76_SCANNING,
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MT76_RESET,
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MT76_OFFCHANNEL,
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MT76_REMOVED,
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MT76_READING_STATS,
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MT76_MORE_STATS,
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};
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struct mt76_hw_cap {
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bool has_2ghz;
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bool has_5ghz;
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};
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struct mt76_driver_ops {
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u16 txwi_size;
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void (*update_survey)(struct mt76_dev *dev);
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int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr,
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struct sk_buff *skb, struct mt76_queue *q,
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struct mt76_wcid *wcid,
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struct ieee80211_sta *sta, u32 *tx_info);
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void (*tx_complete_skb)(struct mt76_dev *dev, struct mt76_queue *q,
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struct mt76_queue_entry *e, bool flush);
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bool (*tx_status_data)(struct mt76_dev *dev, u8 *update);
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void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q,
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struct sk_buff *skb);
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void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q);
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void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta,
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bool ps);
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};
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struct mt76_channel_state {
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u64 cc_active;
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u64 cc_busy;
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};
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struct mt76_sband {
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struct ieee80211_supported_band sband;
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struct mt76_channel_state *chan;
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};
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/* addr req mask */
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#define MT_VEND_TYPE_EEPROM BIT(31)
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#define MT_VEND_TYPE_CFG BIT(30)
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#define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG)
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#define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n))
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enum mt_vendor_req {
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MT_VEND_DEV_MODE = 0x1,
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MT_VEND_WRITE = 0x2,
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MT_VEND_MULTI_WRITE = 0x6,
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MT_VEND_MULTI_READ = 0x7,
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MT_VEND_READ_EEPROM = 0x9,
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MT_VEND_WRITE_FCE = 0x42,
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MT_VEND_WRITE_CFG = 0x46,
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MT_VEND_READ_CFG = 0x47,
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};
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enum mt76u_in_ep {
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MT_EP_IN_PKT_RX,
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MT_EP_IN_CMD_RESP,
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__MT_EP_IN_MAX,
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};
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enum mt76u_out_ep {
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MT_EP_OUT_INBAND_CMD,
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MT_EP_OUT_AC_BK,
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MT_EP_OUT_AC_BE,
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MT_EP_OUT_AC_VI,
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MT_EP_OUT_AC_VO,
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MT_EP_OUT_HCCA,
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__MT_EP_OUT_MAX,
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};
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#define MT_SG_MAX_SIZE 8
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#define MT_NUM_TX_ENTRIES 256
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#define MT_NUM_RX_ENTRIES 128
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#define MCU_RESP_URB_SIZE 1024
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struct mt76_usb {
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struct mutex usb_ctrl_mtx;
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u8 data[32];
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struct tasklet_struct rx_tasklet;
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struct tasklet_struct tx_tasklet;
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struct delayed_work stat_work;
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u8 out_ep[__MT_EP_OUT_MAX];
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u16 out_max_packet;
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u8 in_ep[__MT_EP_IN_MAX];
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u16 in_max_packet;
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struct mt76u_mcu {
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struct mutex mutex;
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struct completion cmpl;
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struct mt76u_buf res;
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u32 msg_seq;
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} mcu;
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};
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struct mt76_dev {
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struct ieee80211_hw *hw;
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struct cfg80211_chan_def chandef;
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struct ieee80211_channel *main_chan;
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spinlock_t lock;
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spinlock_t cc_lock;
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const struct mt76_bus_ops *bus;
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const struct mt76_driver_ops *drv;
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void __iomem *regs;
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struct device *dev;
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struct net_device napi_dev;
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spinlock_t rx_lock;
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struct napi_struct napi[__MT_RXQ_MAX];
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struct sk_buff_head rx_skb[__MT_RXQ_MAX];
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struct list_head txwi_cache;
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struct mt76_queue q_tx[__MT_TXQ_MAX];
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struct mt76_queue q_rx[__MT_RXQ_MAX];
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const struct mt76_queue_ops *queue_ops;
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wait_queue_head_t tx_wait;
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u8 macaddr[ETH_ALEN];
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u32 rev;
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unsigned long state;
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u8 antenna_mask;
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struct mt76_sband sband_2g;
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struct mt76_sband sband_5g;
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struct debugfs_blob_wrapper eeprom;
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struct debugfs_blob_wrapper otp;
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struct mt76_hw_cap cap;
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u32 debugfs_reg;
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struct led_classdev led_cdev;
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char led_name[32];
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bool led_al;
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u8 led_pin;
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struct mt76_usb usb;
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};
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enum mt76_phy_type {
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MT_PHY_TYPE_CCK,
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MT_PHY_TYPE_OFDM,
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MT_PHY_TYPE_HT,
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MT_PHY_TYPE_HT_GF,
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MT_PHY_TYPE_VHT,
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};
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struct mt76_rate_power {
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union {
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struct {
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s8 cck[4];
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s8 ofdm[8];
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s8 ht[16];
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s8 vht[10];
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};
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s8 all[38];
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};
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};
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struct mt76_rx_status {
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struct mt76_wcid *wcid;
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unsigned long reorder_time;
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u8 iv[6];
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u8 aggr:1;
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u8 tid;
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u16 seqno;
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u16 freq;
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u32 flag;
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u8 enc_flags;
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u8 encoding:2, bw:3;
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u8 rate_idx;
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u8 nss;
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u8 band;
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u8 signal;
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u8 chains;
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s8 chain_signal[IEEE80211_MAX_CHAINS];
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};
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#define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__)
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#define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__)
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#define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__)
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#define mt76_wr_copy(dev, ...) (dev)->mt76.bus->copy(&((dev)->mt76), __VA_ARGS__)
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#define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val)
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#define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0)
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#define mt76_get_field(_dev, _reg, _field) \
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FIELD_GET(_field, mt76_rr(dev, _reg))
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#define mt76_rmw_field(_dev, _reg, _field, _val) \
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mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
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#define mt76_hw(dev) (dev)->mt76.hw
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bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
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int timeout);
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#define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__)
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bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
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int timeout);
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#define mt76_poll_msec(dev, ...) __mt76_poll_msec(&((dev)->mt76), __VA_ARGS__)
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void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs);
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static inline u16 mt76_chip(struct mt76_dev *dev)
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{
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return dev->rev >> 16;
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}
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static inline u16 mt76_rev(struct mt76_dev *dev)
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{
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return dev->rev & 0xffff;
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}
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#define mt76xx_chip(dev) mt76_chip(&((dev)->mt76))
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#define mt76xx_rev(dev) mt76_rev(&((dev)->mt76))
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#define mt76_init_queues(dev) (dev)->mt76.queue_ops->init(&((dev)->mt76))
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#define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__)
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#define mt76_queue_add_buf(dev, ...) (dev)->mt76.queue_ops->add_buf(&((dev)->mt76), __VA_ARGS__)
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#define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__)
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#define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__)
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#define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__)
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static inline struct mt76_channel_state *
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mt76_channel_state(struct mt76_dev *dev, struct ieee80211_channel *c)
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{
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struct mt76_sband *msband;
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int idx;
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if (c->band == NL80211_BAND_2GHZ)
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msband = &dev->sband_2g;
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else
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msband = &dev->sband_5g;
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idx = c - &msband->sband.channels[0];
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return &msband->chan[idx];
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}
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struct mt76_dev *mt76_alloc_device(unsigned int size,
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const struct ieee80211_ops *ops);
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int mt76_register_device(struct mt76_dev *dev, bool vht,
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struct ieee80211_rate *rates, int n_rates);
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void mt76_unregister_device(struct mt76_dev *dev);
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struct dentry *mt76_register_debugfs(struct mt76_dev *dev);
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int mt76_eeprom_init(struct mt76_dev *dev, int len);
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void mt76_eeprom_override(struct mt76_dev *dev);
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/* increment with wrap-around */
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static inline int mt76_incr(int val, int size)
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{
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return (val + 1) & (size - 1);
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}
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/* decrement with wrap-around */
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static inline int mt76_decr(int val, int size)
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{
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return (val - 1) & (size - 1);
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}
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/* Hardware uses mirrored order of queues with Q3
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* having the highest priority
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*/
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static inline u8 q2hwq(u8 q)
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{
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return q ^ 0x3;
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}
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static inline struct ieee80211_txq *
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mtxq_to_txq(struct mt76_txq *mtxq)
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{
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void *ptr = mtxq;
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return container_of(ptr, struct ieee80211_txq, drv_priv);
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}
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static inline struct ieee80211_sta *
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wcid_to_sta(struct mt76_wcid *wcid)
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{
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void *ptr = wcid;
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if (!wcid || !wcid->sta)
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return NULL;
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return container_of(ptr, struct ieee80211_sta, drv_priv);
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}
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int mt76_dma_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q,
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struct sk_buff *skb, struct mt76_wcid *wcid,
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struct ieee80211_sta *sta);
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void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb);
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void mt76_tx(struct mt76_dev *dev, struct ieee80211_sta *sta,
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struct mt76_wcid *wcid, struct sk_buff *skb);
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void mt76_txq_init(struct mt76_dev *dev, struct ieee80211_txq *txq);
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void mt76_txq_remove(struct mt76_dev *dev, struct ieee80211_txq *txq);
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void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq);
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void mt76_stop_tx_queues(struct mt76_dev *dev, struct ieee80211_sta *sta,
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bool send_bar);
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void mt76_txq_schedule(struct mt76_dev *dev, struct mt76_queue *hwq);
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void mt76_txq_schedule_all(struct mt76_dev *dev);
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void mt76_release_buffered_frames(struct ieee80211_hw *hw,
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struct ieee80211_sta *sta,
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u16 tids, int nframes,
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enum ieee80211_frame_release_type reason,
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bool more_data);
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void mt76_set_channel(struct mt76_dev *dev);
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int mt76_get_survey(struct ieee80211_hw *hw, int idx,
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struct survey_info *survey);
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void mt76_set_stream_caps(struct mt76_dev *dev, bool vht);
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|
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int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid,
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u16 ssn, u16 size);
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void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid);
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|
|
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void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid,
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struct ieee80211_key_conf *key);
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|
|
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/* internal */
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void mt76_tx_free(struct mt76_dev *dev);
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struct mt76_txwi_cache *mt76_get_txwi(struct mt76_dev *dev);
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void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
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void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames,
|
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struct napi_struct *napi);
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void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
|
|
struct napi_struct *napi);
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void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames);
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|
|
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/* usb */
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static inline bool mt76u_urb_error(struct urb *urb)
|
|
{
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return urb->status &&
|
|
urb->status != -ECONNRESET &&
|
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urb->status != -ESHUTDOWN &&
|
|
urb->status != -ENOENT;
|
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}
|
|
|
|
/* Map hardware queues to usb endpoints */
|
|
static inline u8 q2ep(u8 qid)
|
|
{
|
|
/* TODO: take management packets to queue 5 */
|
|
return qid + 1;
|
|
}
|
|
|
|
static inline bool mt76u_check_sg(struct mt76_dev *dev)
|
|
{
|
|
struct usb_interface *intf = to_usb_interface(dev->dev);
|
|
struct usb_device *udev = interface_to_usbdev(intf);
|
|
|
|
return (udev->bus->sg_tablesize > 0 &&
|
|
(udev->bus->no_sg_constraint ||
|
|
udev->speed == USB_SPEED_WIRELESS));
|
|
}
|
|
|
|
int mt76u_vendor_request(struct mt76_dev *dev, u8 req,
|
|
u8 req_type, u16 val, u16 offset,
|
|
void *buf, size_t len);
|
|
void mt76u_single_wr(struct mt76_dev *dev, const u8 req,
|
|
const u16 offset, const u32 val);
|
|
u32 mt76u_rr(struct mt76_dev *dev, u32 addr);
|
|
void mt76u_wr(struct mt76_dev *dev, u32 addr, u32 val);
|
|
int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf);
|
|
void mt76u_deinit(struct mt76_dev *dev);
|
|
int mt76u_buf_alloc(struct mt76_dev *dev, struct mt76u_buf *buf,
|
|
int nsgs, int len, int sglen, gfp_t gfp);
|
|
void mt76u_buf_free(struct mt76u_buf *buf);
|
|
int mt76u_submit_buf(struct mt76_dev *dev, int dir, int index,
|
|
struct mt76u_buf *buf, gfp_t gfp,
|
|
usb_complete_t complete_fn, void *context);
|
|
int mt76u_submit_rx_buffers(struct mt76_dev *dev);
|
|
int mt76u_alloc_queues(struct mt76_dev *dev);
|
|
void mt76u_stop_queues(struct mt76_dev *dev);
|
|
void mt76u_stop_stat_wk(struct mt76_dev *dev);
|
|
void mt76u_queues_deinit(struct mt76_dev *dev);
|
|
int mt76u_skb_dma_info(struct sk_buff *skb, int port, u32 flags);
|
|
|
|
int mt76u_mcu_fw_send_data(struct mt76_dev *dev, const void *data,
|
|
int data_len, u32 max_payload, u32 offset);
|
|
void mt76u_mcu_complete_urb(struct urb *urb);
|
|
struct sk_buff *mt76u_mcu_msg_alloc(const void *data, int len);
|
|
int mt76u_mcu_send_msg(struct mt76_dev *dev, struct sk_buff *skb,
|
|
int cmd, bool wait_resp);
|
|
void mt76u_mcu_fw_reset(struct mt76_dev *dev);
|
|
int mt76u_mcu_init_rx(struct mt76_dev *dev);
|
|
|
|
#endif
|