6db4831e98
Android 14
975 lines
25 KiB
C
975 lines
25 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* PCI Express PCI Hot Plug Driver
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*
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* Copyright (C) 1995,2001 Compaq Computer Corporation
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* Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
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* Copyright (C) 2001 IBM Corp.
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* Copyright (C) 2003-2004 Intel Corporation
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*
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* All rights reserved.
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*
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* Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/signal.h>
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#include <linux/jiffies.h>
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#include <linux/kthread.h>
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#include <linux/pci.h>
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#include <linux/pm_runtime.h>
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#include <linux/interrupt.h>
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#include <linux/time.h>
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#include <linux/slab.h>
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#include "../pci.h"
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#include "pciehp.h"
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static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
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{
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return ctrl->pcie->port;
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}
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static irqreturn_t pciehp_isr(int irq, void *dev_id);
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static irqreturn_t pciehp_ist(int irq, void *dev_id);
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static int pciehp_poll(void *data);
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static inline int pciehp_request_irq(struct controller *ctrl)
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{
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int retval, irq = ctrl->pcie->irq;
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if (pciehp_poll_mode) {
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ctrl->poll_thread = kthread_run(&pciehp_poll, ctrl,
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"pciehp_poll-%s",
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slot_name(ctrl->slot));
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return PTR_ERR_OR_ZERO(ctrl->poll_thread);
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}
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/* Installs the interrupt handler */
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retval = request_threaded_irq(irq, pciehp_isr, pciehp_ist,
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IRQF_SHARED, MY_NAME, ctrl);
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if (retval)
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ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
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irq);
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return retval;
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}
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static inline void pciehp_free_irq(struct controller *ctrl)
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{
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if (pciehp_poll_mode)
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kthread_stop(ctrl->poll_thread);
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else
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free_irq(ctrl->pcie->irq, ctrl);
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}
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static int pcie_poll_cmd(struct controller *ctrl, int timeout)
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{
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struct pci_dev *pdev = ctrl_dev(ctrl);
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u16 slot_status;
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while (true) {
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pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
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if (slot_status == (u16) ~0) {
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ctrl_info(ctrl, "%s: no response from device\n",
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__func__);
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return 0;
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}
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if (slot_status & PCI_EXP_SLTSTA_CC) {
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pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
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PCI_EXP_SLTSTA_CC);
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return 1;
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}
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if (timeout < 0)
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break;
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msleep(10);
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timeout -= 10;
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}
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return 0; /* timeout */
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}
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static void pcie_wait_cmd(struct controller *ctrl)
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{
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unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
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unsigned long duration = msecs_to_jiffies(msecs);
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unsigned long cmd_timeout = ctrl->cmd_started + duration;
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unsigned long now, timeout;
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int rc;
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/*
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* If the controller does not generate notifications for command
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* completions, we never need to wait between writes.
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*/
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if (NO_CMD_CMPL(ctrl))
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return;
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if (!ctrl->cmd_busy)
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return;
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/*
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* Even if the command has already timed out, we want to call
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* pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
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*/
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now = jiffies;
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if (time_before_eq(cmd_timeout, now))
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timeout = 1;
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else
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timeout = cmd_timeout - now;
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if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
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ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
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rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
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else
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rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
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if (!rc)
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ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
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ctrl->slot_ctrl,
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jiffies_to_msecs(jiffies - ctrl->cmd_started));
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}
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#define CC_ERRATUM_MASK (PCI_EXP_SLTCTL_PCC | \
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PCI_EXP_SLTCTL_PIC | \
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PCI_EXP_SLTCTL_AIC | \
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PCI_EXP_SLTCTL_EIC)
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static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
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u16 mask, bool wait)
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{
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struct pci_dev *pdev = ctrl_dev(ctrl);
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u16 slot_ctrl_orig, slot_ctrl;
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mutex_lock(&ctrl->ctrl_lock);
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/*
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* Always wait for any previous command that might still be in progress
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*/
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pcie_wait_cmd(ctrl);
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pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
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if (slot_ctrl == (u16) ~0) {
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ctrl_info(ctrl, "%s: no response from device\n", __func__);
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goto out;
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}
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slot_ctrl_orig = slot_ctrl;
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slot_ctrl &= ~mask;
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slot_ctrl |= (cmd & mask);
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ctrl->cmd_busy = 1;
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smp_mb();
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pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
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ctrl->cmd_started = jiffies;
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ctrl->slot_ctrl = slot_ctrl;
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/*
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* Controllers with the Intel CF118 and similar errata advertise
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* Command Completed support, but they only set Command Completed
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* if we change the "Control" bits for power, power indicator,
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* attention indicator, or interlock. If we only change the
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* "Enable" bits, they never set the Command Completed bit.
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*/
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if (pdev->broken_cmd_compl &&
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(slot_ctrl_orig & CC_ERRATUM_MASK) == (slot_ctrl & CC_ERRATUM_MASK))
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ctrl->cmd_busy = 0;
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/*
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* Optionally wait for the hardware to be ready for a new command,
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* indicating completion of the above issued command.
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*/
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if (wait)
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pcie_wait_cmd(ctrl);
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out:
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mutex_unlock(&ctrl->ctrl_lock);
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}
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/**
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* pcie_write_cmd - Issue controller command
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* @ctrl: controller to which the command is issued
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* @cmd: command value written to slot control register
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* @mask: bitmask of slot control register to be modified
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*/
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static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
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{
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pcie_do_write_cmd(ctrl, cmd, mask, true);
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}
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/* Same as above without waiting for the hardware to latch */
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static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
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{
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pcie_do_write_cmd(ctrl, cmd, mask, false);
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}
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bool pciehp_check_link_active(struct controller *ctrl)
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{
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struct pci_dev *pdev = ctrl_dev(ctrl);
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u16 lnk_status;
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bool ret;
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pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
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ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
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if (ret)
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ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
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return ret;
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}
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static void pcie_wait_link_active(struct controller *ctrl)
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{
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struct pci_dev *pdev = ctrl_dev(ctrl);
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pcie_wait_for_link(pdev, true);
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}
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static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
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{
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u32 l;
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int count = 0;
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int delay = 1000, step = 20;
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bool found = false;
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do {
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found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
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count++;
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if (found)
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break;
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msleep(step);
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delay -= step;
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} while (delay > 0);
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if (count > 1 && pciehp_debug)
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printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
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pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
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PCI_FUNC(devfn), count, step, l);
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return found;
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}
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int pciehp_check_link_status(struct controller *ctrl)
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{
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struct pci_dev *pdev = ctrl_dev(ctrl);
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bool found;
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u16 lnk_status;
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/*
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* Data Link Layer Link Active Reporting must be capable for
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* hot-plug capable downstream port. But old controller might
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* not implement it. In this case, we wait for 1000 ms.
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*/
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if (ctrl->link_active_reporting)
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pcie_wait_link_active(ctrl);
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else
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msleep(1000);
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/* wait 100ms before read pci conf, and try in 1s */
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msleep(100);
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found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
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PCI_DEVFN(0, 0));
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/* ignore link or presence changes up to this point */
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if (found)
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atomic_and(~(PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC),
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&ctrl->pending_events);
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pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
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ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
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if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
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!(lnk_status & PCI_EXP_LNKSTA_NLW)) {
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ctrl_err(ctrl, "link training error: status %#06x\n",
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lnk_status);
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return -1;
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}
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pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
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if (!found)
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return -1;
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return 0;
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}
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static int __pciehp_link_set(struct controller *ctrl, bool enable)
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{
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struct pci_dev *pdev = ctrl_dev(ctrl);
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u16 lnk_ctrl;
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pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
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if (enable)
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lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
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else
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lnk_ctrl |= PCI_EXP_LNKCTL_LD;
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pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
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ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
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return 0;
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}
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static int pciehp_link_enable(struct controller *ctrl)
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{
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return __pciehp_link_set(ctrl, true);
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}
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int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot,
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u8 *status)
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{
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struct slot *slot = hotplug_slot->private;
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struct pci_dev *pdev = ctrl_dev(slot->ctrl);
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u16 slot_ctrl;
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pci_config_pm_runtime_get(pdev);
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pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
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pci_config_pm_runtime_put(pdev);
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*status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6;
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return 0;
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}
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void pciehp_get_attention_status(struct slot *slot, u8 *status)
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{
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struct controller *ctrl = slot->ctrl;
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struct pci_dev *pdev = ctrl_dev(ctrl);
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u16 slot_ctrl;
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pci_config_pm_runtime_get(pdev);
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pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
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pci_config_pm_runtime_put(pdev);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
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pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
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switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
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case PCI_EXP_SLTCTL_ATTN_IND_ON:
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*status = 1; /* On */
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break;
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case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
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*status = 2; /* Blink */
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break;
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case PCI_EXP_SLTCTL_ATTN_IND_OFF:
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*status = 0; /* Off */
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break;
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default:
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*status = 0xFF;
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break;
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}
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}
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void pciehp_get_power_status(struct slot *slot, u8 *status)
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{
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struct controller *ctrl = slot->ctrl;
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struct pci_dev *pdev = ctrl_dev(ctrl);
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u16 slot_ctrl;
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pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
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pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
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switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
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case PCI_EXP_SLTCTL_PWR_ON:
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*status = 1; /* On */
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break;
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case PCI_EXP_SLTCTL_PWR_OFF:
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*status = 0; /* Off */
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break;
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default:
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*status = 0xFF;
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break;
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}
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}
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void pciehp_get_latch_status(struct slot *slot, u8 *status)
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{
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struct pci_dev *pdev = ctrl_dev(slot->ctrl);
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u16 slot_status;
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pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
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*status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
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}
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void pciehp_get_adapter_status(struct slot *slot, u8 *status)
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{
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struct pci_dev *pdev = ctrl_dev(slot->ctrl);
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u16 slot_status;
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pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
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*status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
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}
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int pciehp_query_power_fault(struct slot *slot)
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{
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struct pci_dev *pdev = ctrl_dev(slot->ctrl);
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u16 slot_status;
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pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
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return !!(slot_status & PCI_EXP_SLTSTA_PFD);
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}
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int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot,
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u8 status)
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{
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struct slot *slot = hotplug_slot->private;
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struct controller *ctrl = slot->ctrl;
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struct pci_dev *pdev = ctrl_dev(ctrl);
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pci_config_pm_runtime_get(pdev);
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pcie_write_cmd_nowait(ctrl, status << 6,
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PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC);
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pci_config_pm_runtime_put(pdev);
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return 0;
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}
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void pciehp_set_attention_status(struct slot *slot, u8 value)
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{
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struct controller *ctrl = slot->ctrl;
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u16 slot_cmd;
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if (!ATTN_LED(ctrl))
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return;
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switch (value) {
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case 0: /* turn off */
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slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
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break;
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case 1: /* turn on */
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slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
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break;
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case 2: /* turn blink */
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slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
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break;
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default:
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return;
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}
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pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
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}
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void pciehp_green_led_on(struct slot *slot)
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{
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struct controller *ctrl = slot->ctrl;
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if (!PWR_LED(ctrl))
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return;
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pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON,
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PCI_EXP_SLTCTL_PIC);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
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PCI_EXP_SLTCTL_PWR_IND_ON);
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}
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void pciehp_green_led_off(struct slot *slot)
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{
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struct controller *ctrl = slot->ctrl;
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if (!PWR_LED(ctrl))
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return;
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pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
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PCI_EXP_SLTCTL_PIC);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
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PCI_EXP_SLTCTL_PWR_IND_OFF);
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}
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void pciehp_green_led_blink(struct slot *slot)
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{
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struct controller *ctrl = slot->ctrl;
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if (!PWR_LED(ctrl))
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return;
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pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK,
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PCI_EXP_SLTCTL_PIC);
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ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
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PCI_EXP_SLTCTL_PWR_IND_BLINK);
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}
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int pciehp_power_on_slot(struct slot *slot)
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{
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struct controller *ctrl = slot->ctrl;
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struct pci_dev *pdev = ctrl_dev(ctrl);
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u16 slot_status;
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int retval;
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/* Clear power-fault bit from previous power failures */
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pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
|
|
if (slot_status & PCI_EXP_SLTSTA_PFD)
|
|
pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
|
|
PCI_EXP_SLTSTA_PFD);
|
|
ctrl->power_fault_detected = 0;
|
|
|
|
pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
|
|
PCI_EXP_SLTCTL_PWR_ON);
|
|
|
|
retval = pciehp_link_enable(ctrl);
|
|
if (retval)
|
|
ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
|
|
|
|
return retval;
|
|
}
|
|
|
|
void pciehp_power_off_slot(struct slot *slot)
|
|
{
|
|
struct controller *ctrl = slot->ctrl;
|
|
|
|
pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
|
|
PCI_EXP_SLTCTL_PWR_OFF);
|
|
}
|
|
|
|
static irqreturn_t pciehp_isr(int irq, void *dev_id)
|
|
{
|
|
struct controller *ctrl = (struct controller *)dev_id;
|
|
struct pci_dev *pdev = ctrl_dev(ctrl);
|
|
struct device *parent = pdev->dev.parent;
|
|
u16 status, events = 0;
|
|
|
|
/*
|
|
* Interrupts only occur in D3hot or shallower (PCIe r4.0, sec 6.7.3.4).
|
|
*/
|
|
if (pdev->current_state == PCI_D3cold)
|
|
return IRQ_NONE;
|
|
|
|
/*
|
|
* Keep the port accessible by holding a runtime PM ref on its parent.
|
|
* Defer resume of the parent to the IRQ thread if it's suspended.
|
|
* Mask the interrupt until then.
|
|
*/
|
|
if (parent) {
|
|
pm_runtime_get_noresume(parent);
|
|
if (!pm_runtime_active(parent)) {
|
|
pm_runtime_put(parent);
|
|
disable_irq_nosync(irq);
|
|
atomic_or(RERUN_ISR, &ctrl->pending_events);
|
|
return IRQ_WAKE_THREAD;
|
|
}
|
|
}
|
|
|
|
read_status:
|
|
pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status);
|
|
if (status == (u16) ~0) {
|
|
ctrl_info(ctrl, "%s: no response from device\n", __func__);
|
|
if (parent)
|
|
pm_runtime_put(parent);
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
/*
|
|
* Slot Status contains plain status bits as well as event
|
|
* notification bits; right now we only want the event bits.
|
|
*/
|
|
status &= PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
|
|
PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC |
|
|
PCI_EXP_SLTSTA_DLLSC;
|
|
|
|
/*
|
|
* If we've already reported a power fault, don't report it again
|
|
* until we've done something to handle it.
|
|
*/
|
|
if (ctrl->power_fault_detected)
|
|
status &= ~PCI_EXP_SLTSTA_PFD;
|
|
|
|
events |= status;
|
|
if (!events) {
|
|
if (parent)
|
|
pm_runtime_put(parent);
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
if (status) {
|
|
pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, events);
|
|
|
|
/*
|
|
* In MSI mode, all event bits must be zero before the port
|
|
* will send a new interrupt (PCIe Base Spec r5.0 sec 6.7.3.4).
|
|
* So re-read the Slot Status register in case a bit was set
|
|
* between read and write.
|
|
*/
|
|
if (pci_dev_msi_enabled(pdev) && !pciehp_poll_mode)
|
|
goto read_status;
|
|
}
|
|
|
|
ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events);
|
|
if (parent)
|
|
pm_runtime_put(parent);
|
|
|
|
/*
|
|
* Command Completed notifications are not deferred to the
|
|
* IRQ thread because it may be waiting for their arrival.
|
|
*/
|
|
if (events & PCI_EXP_SLTSTA_CC) {
|
|
ctrl->cmd_busy = 0;
|
|
smp_mb();
|
|
wake_up(&ctrl->queue);
|
|
|
|
if (events == PCI_EXP_SLTSTA_CC)
|
|
return IRQ_HANDLED;
|
|
|
|
events &= ~PCI_EXP_SLTSTA_CC;
|
|
}
|
|
|
|
if (pdev->ignore_hotplug) {
|
|
ctrl_dbg(ctrl, "ignoring hotplug event %#06x\n", events);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
/* Save pending events for consumption by IRQ thread. */
|
|
atomic_or(events, &ctrl->pending_events);
|
|
return IRQ_WAKE_THREAD;
|
|
}
|
|
|
|
static irqreturn_t pciehp_ist(int irq, void *dev_id)
|
|
{
|
|
struct controller *ctrl = (struct controller *)dev_id;
|
|
struct pci_dev *pdev = ctrl_dev(ctrl);
|
|
struct slot *slot = ctrl->slot;
|
|
irqreturn_t ret;
|
|
u32 events;
|
|
|
|
ctrl->ist_running = true;
|
|
pci_config_pm_runtime_get(pdev);
|
|
|
|
/* rerun pciehp_isr() if the port was inaccessible on interrupt */
|
|
if (atomic_fetch_and(~RERUN_ISR, &ctrl->pending_events) & RERUN_ISR) {
|
|
ret = pciehp_isr(irq, dev_id);
|
|
enable_irq(irq);
|
|
if (ret != IRQ_WAKE_THREAD)
|
|
goto out;
|
|
}
|
|
|
|
synchronize_hardirq(irq);
|
|
events = atomic_xchg(&ctrl->pending_events, 0);
|
|
if (!events) {
|
|
ret = IRQ_NONE;
|
|
goto out;
|
|
}
|
|
|
|
/* Check Attention Button Pressed */
|
|
if (events & PCI_EXP_SLTSTA_ABP) {
|
|
ctrl_info(ctrl, "Slot(%s): Attention button pressed\n",
|
|
slot_name(slot));
|
|
pciehp_handle_button_press(slot);
|
|
}
|
|
|
|
/* Check Power Fault Detected */
|
|
if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
|
|
ctrl->power_fault_detected = 1;
|
|
ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(slot));
|
|
pciehp_set_attention_status(slot, 1);
|
|
pciehp_green_led_off(slot);
|
|
}
|
|
|
|
/*
|
|
* Disable requests have higher priority than Presence Detect Changed
|
|
* or Data Link Layer State Changed events.
|
|
*/
|
|
down_read(&ctrl->reset_lock);
|
|
if (events & DISABLE_SLOT)
|
|
pciehp_handle_disable_request(slot);
|
|
else if (events & (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC))
|
|
pciehp_handle_presence_or_link_change(slot, events);
|
|
up_read(&ctrl->reset_lock);
|
|
|
|
ret = IRQ_HANDLED;
|
|
out:
|
|
pci_config_pm_runtime_put(pdev);
|
|
ctrl->ist_running = false;
|
|
wake_up(&ctrl->requester);
|
|
return ret;
|
|
}
|
|
|
|
static int pciehp_poll(void *data)
|
|
{
|
|
struct controller *ctrl = data;
|
|
|
|
schedule_timeout_idle(10 * HZ); /* start with 10 sec delay */
|
|
|
|
while (!kthread_should_stop()) {
|
|
/* poll for interrupt events or user requests */
|
|
while (pciehp_isr(IRQ_NOTCONNECTED, ctrl) == IRQ_WAKE_THREAD ||
|
|
atomic_read(&ctrl->pending_events))
|
|
pciehp_ist(IRQ_NOTCONNECTED, ctrl);
|
|
|
|
if (pciehp_poll_time <= 0 || pciehp_poll_time > 60)
|
|
pciehp_poll_time = 2; /* clamp to sane value */
|
|
|
|
schedule_timeout_idle(pciehp_poll_time * HZ);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void pcie_enable_notification(struct controller *ctrl)
|
|
{
|
|
u16 cmd, mask;
|
|
|
|
/*
|
|
* TBD: Power fault detected software notification support.
|
|
*
|
|
* Power fault detected software notification is not enabled
|
|
* now, because it caused power fault detected interrupt storm
|
|
* on some machines. On those machines, power fault detected
|
|
* bit in the slot status register was set again immediately
|
|
* when it is cleared in the interrupt service routine, and
|
|
* next power fault detected interrupt was notified again.
|
|
*/
|
|
|
|
/*
|
|
* Always enable link events: thus link-up and link-down shall
|
|
* always be treated as hotplug and unplug respectively. Enable
|
|
* presence detect only if Attention Button is not present.
|
|
*/
|
|
cmd = PCI_EXP_SLTCTL_DLLSCE;
|
|
if (ATTN_BUTTN(ctrl))
|
|
cmd |= PCI_EXP_SLTCTL_ABPE;
|
|
else
|
|
cmd |= PCI_EXP_SLTCTL_PDCE;
|
|
if (!pciehp_poll_mode)
|
|
cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
|
|
|
|
mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
|
|
PCI_EXP_SLTCTL_PFDE |
|
|
PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
|
|
PCI_EXP_SLTCTL_DLLSCE);
|
|
|
|
pcie_write_cmd_nowait(ctrl, cmd, mask);
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
|
|
}
|
|
|
|
static void pcie_disable_notification(struct controller *ctrl)
|
|
{
|
|
u16 mask;
|
|
|
|
mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
|
|
PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
|
|
PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
|
|
PCI_EXP_SLTCTL_DLLSCE);
|
|
pcie_write_cmd(ctrl, 0, mask);
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
|
|
}
|
|
|
|
void pcie_clear_hotplug_events(struct controller *ctrl)
|
|
{
|
|
pcie_capability_write_word(ctrl_dev(ctrl), PCI_EXP_SLTSTA,
|
|
PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC);
|
|
}
|
|
|
|
/*
|
|
* pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
|
|
* bus reset of the bridge, but at the same time we want to ensure that it is
|
|
* not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
|
|
* disable link state notification and presence detection change notification
|
|
* momentarily, if we see that they could interfere. Also, clear any spurious
|
|
* events after.
|
|
*/
|
|
int pciehp_reset_slot(struct slot *slot, int probe)
|
|
{
|
|
struct controller *ctrl = slot->ctrl;
|
|
struct pci_dev *pdev = ctrl_dev(ctrl);
|
|
u16 stat_mask = 0, ctrl_mask = 0;
|
|
int rc;
|
|
|
|
if (probe)
|
|
return 0;
|
|
|
|
down_write(&ctrl->reset_lock);
|
|
|
|
if (!ATTN_BUTTN(ctrl)) {
|
|
ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
|
|
stat_mask |= PCI_EXP_SLTSTA_PDC;
|
|
}
|
|
ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
|
|
stat_mask |= PCI_EXP_SLTSTA_DLLSC;
|
|
|
|
pcie_write_cmd(ctrl, 0, ctrl_mask);
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
|
|
|
|
rc = pci_bridge_secondary_bus_reset(ctrl->pcie->port);
|
|
|
|
pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
|
|
pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
|
|
|
|
up_write(&ctrl->reset_lock);
|
|
return rc;
|
|
}
|
|
|
|
int pcie_init_notification(struct controller *ctrl)
|
|
{
|
|
if (pciehp_request_irq(ctrl))
|
|
return -1;
|
|
pcie_enable_notification(ctrl);
|
|
ctrl->notification_enabled = 1;
|
|
return 0;
|
|
}
|
|
|
|
void pcie_shutdown_notification(struct controller *ctrl)
|
|
{
|
|
if (ctrl->notification_enabled) {
|
|
pcie_disable_notification(ctrl);
|
|
pciehp_free_irq(ctrl);
|
|
ctrl->notification_enabled = 0;
|
|
}
|
|
}
|
|
|
|
static int pcie_init_slot(struct controller *ctrl)
|
|
{
|
|
struct pci_bus *subordinate = ctrl_dev(ctrl)->subordinate;
|
|
struct slot *slot;
|
|
|
|
slot = kzalloc(sizeof(*slot), GFP_KERNEL);
|
|
if (!slot)
|
|
return -ENOMEM;
|
|
|
|
down_read(&pci_bus_sem);
|
|
slot->state = list_empty(&subordinate->devices) ? OFF_STATE : ON_STATE;
|
|
up_read(&pci_bus_sem);
|
|
|
|
slot->ctrl = ctrl;
|
|
mutex_init(&slot->lock);
|
|
INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
|
|
ctrl->slot = slot;
|
|
return 0;
|
|
}
|
|
|
|
static void pcie_cleanup_slot(struct controller *ctrl)
|
|
{
|
|
struct slot *slot = ctrl->slot;
|
|
|
|
cancel_delayed_work_sync(&slot->work);
|
|
kfree(slot);
|
|
}
|
|
|
|
static inline void dbg_ctrl(struct controller *ctrl)
|
|
{
|
|
struct pci_dev *pdev = ctrl->pcie->port;
|
|
u16 reg16;
|
|
|
|
if (!pciehp_debug)
|
|
return;
|
|
|
|
ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
|
|
pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16);
|
|
ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
|
|
pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16);
|
|
ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
|
|
}
|
|
|
|
#define FLAG(x, y) (((x) & (y)) ? '+' : '-')
|
|
|
|
struct controller *pcie_init(struct pcie_device *dev)
|
|
{
|
|
struct controller *ctrl;
|
|
u32 slot_cap, link_cap;
|
|
u8 occupied, poweron;
|
|
struct pci_dev *pdev = dev->port;
|
|
|
|
ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
|
|
if (!ctrl)
|
|
goto abort;
|
|
|
|
ctrl->pcie = dev;
|
|
pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
|
|
|
|
if (pdev->hotplug_user_indicators)
|
|
slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP);
|
|
|
|
/*
|
|
* We assume no Thunderbolt controllers support Command Complete events,
|
|
* but some controllers falsely claim they do.
|
|
*/
|
|
if (pdev->is_thunderbolt)
|
|
slot_cap |= PCI_EXP_SLTCAP_NCCS;
|
|
|
|
ctrl->slot_cap = slot_cap;
|
|
mutex_init(&ctrl->ctrl_lock);
|
|
init_rwsem(&ctrl->reset_lock);
|
|
init_waitqueue_head(&ctrl->requester);
|
|
init_waitqueue_head(&ctrl->queue);
|
|
dbg_ctrl(ctrl);
|
|
|
|
/* Check if Data Link Layer Link Active Reporting is implemented */
|
|
pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
|
|
if (link_cap & PCI_EXP_LNKCAP_DLLLARC)
|
|
ctrl->link_active_reporting = 1;
|
|
|
|
/* Clear all remaining event bits in Slot Status register. */
|
|
pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
|
|
PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
|
|
PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_CC |
|
|
PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC);
|
|
|
|
ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c%s\n",
|
|
(slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
|
|
FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC),
|
|
pdev->broken_cmd_compl ? " (with Cmd Compl erratum)" : "");
|
|
|
|
if (pcie_init_slot(ctrl))
|
|
goto abort_ctrl;
|
|
|
|
/*
|
|
* If empty slot's power status is on, turn power off. The IRQ isn't
|
|
* requested yet, so avoid triggering a notification with this command.
|
|
*/
|
|
if (POWER_CTRL(ctrl)) {
|
|
pciehp_get_adapter_status(ctrl->slot, &occupied);
|
|
pciehp_get_power_status(ctrl->slot, &poweron);
|
|
if (!occupied && poweron) {
|
|
pcie_disable_notification(ctrl);
|
|
pciehp_power_off_slot(ctrl->slot);
|
|
}
|
|
}
|
|
|
|
return ctrl;
|
|
|
|
abort_ctrl:
|
|
kfree(ctrl);
|
|
abort:
|
|
return NULL;
|
|
}
|
|
|
|
void pciehp_release_ctrl(struct controller *ctrl)
|
|
{
|
|
pcie_cleanup_slot(ctrl);
|
|
kfree(ctrl);
|
|
}
|
|
|
|
static void quirk_cmd_compl(struct pci_dev *pdev)
|
|
{
|
|
u32 slot_cap;
|
|
|
|
if (pci_is_pcie(pdev)) {
|
|
pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
|
|
if (slot_cap & PCI_EXP_SLTCAP_HPC &&
|
|
!(slot_cap & PCI_EXP_SLTCAP_NCCS))
|
|
pdev->broken_cmd_compl = 1;
|
|
}
|
|
}
|
|
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
|
|
PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
|
|
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0400,
|
|
PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
|
|
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0401,
|
|
PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
|