378 lines
9 KiB
C
378 lines
9 KiB
C
/*
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* Copyright 2017 Impinj, Inc
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* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
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*
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* Based on the code of analogus driver:
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*
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* Copyright 2015-2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <dt-bindings/power/imx7-power.h>
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#define GPC_LPCR_A7_BSC 0x000
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#define GPC_PGC_CPU_MAPPING 0x0ec
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#define USB_HSIC_PHY_A7_DOMAIN BIT(6)
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#define USB_OTG2_PHY_A7_DOMAIN BIT(5)
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#define USB_OTG1_PHY_A7_DOMAIN BIT(4)
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#define PCIE_PHY_A7_DOMAIN BIT(3)
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#define MIPI_PHY_A7_DOMAIN BIT(2)
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#define GPC_PU_PGC_SW_PUP_REQ 0x0f8
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#define GPC_PU_PGC_SW_PDN_REQ 0x104
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#define USB_HSIC_PHY_SW_Pxx_REQ BIT(4)
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#define USB_OTG2_PHY_SW_Pxx_REQ BIT(3)
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#define USB_OTG1_PHY_SW_Pxx_REQ BIT(2)
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#define PCIE_PHY_SW_Pxx_REQ BIT(1)
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#define MIPI_PHY_SW_Pxx_REQ BIT(0)
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#define GPC_M4_PU_PDN_FLG 0x1bc
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/*
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* The PGC offset values in Reference Manual
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* (Rev. 1, 01/2018 and the older ones) GPC chapter's
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* GPC_PGC memory map are incorrect, below offset
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* values are from design RTL.
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*/
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#define PGC_MIPI 16
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#define PGC_PCIE 17
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#define PGC_USB_HSIC 20
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#define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
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#define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
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#define GPC_PGC_CTRL_PCR BIT(0)
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struct imx7_pgc_domain {
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struct generic_pm_domain genpd;
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struct regmap *regmap;
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struct regulator *regulator;
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unsigned int pgc;
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const struct {
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u32 pxx;
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u32 map;
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} bits;
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const int voltage;
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struct device *dev;
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};
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static int imx7_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
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bool on)
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{
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struct imx7_pgc_domain *domain = container_of(genpd,
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struct imx7_pgc_domain,
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genpd);
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unsigned int offset = on ?
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GPC_PU_PGC_SW_PUP_REQ : GPC_PU_PGC_SW_PDN_REQ;
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const bool enable_power_control = !on;
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const bool has_regulator = !IS_ERR(domain->regulator);
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unsigned long deadline;
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int ret = 0;
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regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
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domain->bits.map, domain->bits.map);
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if (has_regulator && on) {
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ret = regulator_enable(domain->regulator);
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if (ret) {
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dev_err(domain->dev, "failed to enable regulator\n");
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goto unmap;
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}
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}
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if (enable_power_control)
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regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
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GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
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regmap_update_bits(domain->regmap, offset,
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domain->bits.pxx, domain->bits.pxx);
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/*
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* As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
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* for PUP_REQ/PDN_REQ bit to be cleared
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*/
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deadline = jiffies + msecs_to_jiffies(1);
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while (true) {
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u32 pxx_req;
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regmap_read(domain->regmap, offset, &pxx_req);
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if (!(pxx_req & domain->bits.pxx))
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break;
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if (time_after(jiffies, deadline)) {
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dev_err(domain->dev, "falied to command PGC\n");
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ret = -ETIMEDOUT;
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/*
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* If we were in a process of enabling a
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* domain and failed we might as well disable
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* the regulator we just enabled. And if it
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* was the opposite situation and we failed to
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* power down -- keep the regulator on
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*/
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on = !on;
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break;
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}
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cpu_relax();
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}
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if (enable_power_control)
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regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
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GPC_PGC_CTRL_PCR, 0);
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if (has_regulator && !on) {
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int err;
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err = regulator_disable(domain->regulator);
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if (err)
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dev_err(domain->dev,
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"failed to disable regulator: %d\n", ret);
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/* Preserve earlier error code */
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ret = ret ?: err;
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}
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unmap:
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regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
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domain->bits.map, 0);
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return ret;
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}
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static int imx7_gpc_pu_pgc_sw_pup_req(struct generic_pm_domain *genpd)
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{
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return imx7_gpc_pu_pgc_sw_pxx_req(genpd, true);
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}
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static int imx7_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd)
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{
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return imx7_gpc_pu_pgc_sw_pxx_req(genpd, false);
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}
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static const struct imx7_pgc_domain imx7_pgc_domains[] = {
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[IMX7_POWER_DOMAIN_MIPI_PHY] = {
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.genpd = {
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.name = "mipi-phy",
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},
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.bits = {
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.pxx = MIPI_PHY_SW_Pxx_REQ,
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.map = MIPI_PHY_A7_DOMAIN,
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},
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.voltage = 1000000,
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.pgc = PGC_MIPI,
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},
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[IMX7_POWER_DOMAIN_PCIE_PHY] = {
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.genpd = {
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.name = "pcie-phy",
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},
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.bits = {
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.pxx = PCIE_PHY_SW_Pxx_REQ,
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.map = PCIE_PHY_A7_DOMAIN,
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},
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.voltage = 1000000,
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.pgc = PGC_PCIE,
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},
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[IMX7_POWER_DOMAIN_USB_HSIC_PHY] = {
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.genpd = {
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.name = "usb-hsic-phy",
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},
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.bits = {
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.pxx = USB_HSIC_PHY_SW_Pxx_REQ,
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.map = USB_HSIC_PHY_A7_DOMAIN,
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},
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.voltage = 1200000,
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.pgc = PGC_USB_HSIC,
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},
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};
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static int imx7_pgc_domain_probe(struct platform_device *pdev)
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{
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struct imx7_pgc_domain *domain = pdev->dev.platform_data;
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int ret;
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domain->dev = &pdev->dev;
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domain->regulator = devm_regulator_get_optional(domain->dev, "power");
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if (IS_ERR(domain->regulator)) {
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if (PTR_ERR(domain->regulator) != -ENODEV) {
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if (PTR_ERR(domain->regulator) != -EPROBE_DEFER)
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dev_err(domain->dev, "Failed to get domain's regulator\n");
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return PTR_ERR(domain->regulator);
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}
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} else {
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regulator_set_voltage(domain->regulator,
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domain->voltage, domain->voltage);
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}
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ret = pm_genpd_init(&domain->genpd, NULL, true);
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if (ret) {
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dev_err(domain->dev, "Failed to init power domain\n");
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return ret;
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}
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ret = of_genpd_add_provider_simple(domain->dev->of_node,
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&domain->genpd);
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if (ret) {
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dev_err(domain->dev, "Failed to add genpd provider\n");
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pm_genpd_remove(&domain->genpd);
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}
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return ret;
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}
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static int imx7_pgc_domain_remove(struct platform_device *pdev)
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{
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struct imx7_pgc_domain *domain = pdev->dev.platform_data;
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of_genpd_del_provider(domain->dev->of_node);
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pm_genpd_remove(&domain->genpd);
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return 0;
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}
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static const struct platform_device_id imx7_pgc_domain_id[] = {
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{ "imx7-pgc-domain", },
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{ },
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};
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static struct platform_driver imx7_pgc_domain_driver = {
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.driver = {
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.name = "imx7-pgc",
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},
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.probe = imx7_pgc_domain_probe,
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.remove = imx7_pgc_domain_remove,
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.id_table = imx7_pgc_domain_id,
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};
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builtin_platform_driver(imx7_pgc_domain_driver)
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static int imx_gpcv2_probe(struct platform_device *pdev)
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{
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static const struct regmap_range yes_ranges[] = {
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regmap_reg_range(GPC_LPCR_A7_BSC,
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GPC_M4_PU_PDN_FLG),
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regmap_reg_range(GPC_PGC_CTRL(PGC_MIPI),
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GPC_PGC_SR(PGC_MIPI)),
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regmap_reg_range(GPC_PGC_CTRL(PGC_PCIE),
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GPC_PGC_SR(PGC_PCIE)),
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regmap_reg_range(GPC_PGC_CTRL(PGC_USB_HSIC),
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GPC_PGC_SR(PGC_USB_HSIC)),
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};
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static const struct regmap_access_table access_table = {
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.yes_ranges = yes_ranges,
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.n_yes_ranges = ARRAY_SIZE(yes_ranges),
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};
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static const struct regmap_config regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.rd_table = &access_table,
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.wr_table = &access_table,
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.max_register = SZ_4K,
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};
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struct device *dev = &pdev->dev;
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struct device_node *pgc_np, *np;
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struct regmap *regmap;
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struct resource *res;
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void __iomem *base;
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int ret;
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pgc_np = of_get_child_by_name(dev->of_node, "pgc");
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if (!pgc_np) {
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dev_err(dev, "No power domains specified in DT\n");
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return -EINVAL;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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regmap = devm_regmap_init_mmio(dev, base, ®map_config);
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if (IS_ERR(regmap)) {
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ret = PTR_ERR(regmap);
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dev_err(dev, "failed to init regmap (%d)\n", ret);
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return ret;
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}
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for_each_child_of_node(pgc_np, np) {
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struct platform_device *pd_pdev;
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struct imx7_pgc_domain *domain;
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u32 domain_index;
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ret = of_property_read_u32(np, "reg", &domain_index);
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if (ret) {
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dev_err(dev, "Failed to read 'reg' property\n");
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of_node_put(np);
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return ret;
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}
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if (domain_index >= ARRAY_SIZE(imx7_pgc_domains)) {
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dev_warn(dev,
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"Domain index %d is out of bounds\n",
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domain_index);
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continue;
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}
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pd_pdev = platform_device_alloc("imx7-pgc-domain",
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domain_index);
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if (!pd_pdev) {
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dev_err(dev, "Failed to allocate platform device\n");
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of_node_put(np);
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return -ENOMEM;
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}
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ret = platform_device_add_data(pd_pdev,
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&imx7_pgc_domains[domain_index],
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sizeof(imx7_pgc_domains[domain_index]));
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if (ret) {
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platform_device_put(pd_pdev);
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of_node_put(np);
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return ret;
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}
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domain = pd_pdev->dev.platform_data;
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domain->regmap = regmap;
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domain->genpd.power_on = imx7_gpc_pu_pgc_sw_pup_req;
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domain->genpd.power_off = imx7_gpc_pu_pgc_sw_pdn_req;
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pd_pdev->dev.parent = dev;
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pd_pdev->dev.of_node = np;
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ret = platform_device_add(pd_pdev);
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if (ret) {
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platform_device_put(pd_pdev);
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of_node_put(np);
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return ret;
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}
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}
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return 0;
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}
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static const struct of_device_id imx_gpcv2_dt_ids[] = {
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{ .compatible = "fsl,imx7d-gpc" },
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{ }
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};
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static struct platform_driver imx_gpc_driver = {
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.driver = {
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.name = "imx-gpcv2",
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.of_match_table = imx_gpcv2_dt_ids,
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},
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.probe = imx_gpcv2_probe,
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};
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builtin_platform_driver(imx_gpc_driver)
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