818 lines
28 KiB
C
818 lines
28 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* hcd.h - DesignWare HS OTG Controller host-mode declarations
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*
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* Copyright (C) 2004-2013 Synopsys, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The names of the above-listed copyright holders may not be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __DWC2_HCD_H__
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#define __DWC2_HCD_H__
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/*
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* This file contains the structures, constants, and interfaces for the
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* Host Contoller Driver (HCD)
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*
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* The Host Controller Driver (HCD) is responsible for translating requests
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* from the USB Driver into the appropriate actions on the DWC_otg controller.
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* It isolates the USBD from the specifics of the controller by providing an
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* API to the USBD.
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*/
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struct dwc2_qh;
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/**
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* struct dwc2_host_chan - Software host channel descriptor
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*
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* @hc_num: Host channel number, used for register address lookup
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* @dev_addr: Address of the device
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* @ep_num: Endpoint of the device
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* @ep_is_in: Endpoint direction
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* @speed: Device speed. One of the following values:
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* - USB_SPEED_LOW
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* - USB_SPEED_FULL
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* - USB_SPEED_HIGH
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* @ep_type: Endpoint type. One of the following values:
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* - USB_ENDPOINT_XFER_CONTROL: 0
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* - USB_ENDPOINT_XFER_ISOC: 1
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* - USB_ENDPOINT_XFER_BULK: 2
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* - USB_ENDPOINT_XFER_INTR: 3
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* @max_packet: Max packet size in bytes
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* @data_pid_start: PID for initial transaction.
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* 0: DATA0
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* 1: DATA2
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* 2: DATA1
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* 3: MDATA (non-Control EP),
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* SETUP (Control EP)
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* @multi_count: Number of additional periodic transactions per
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* (micro)frame
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* @xfer_buf: Pointer to current transfer buffer position
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* @xfer_dma: DMA address of xfer_buf
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* @align_buf: In Buffer DMA mode this will be used if xfer_buf is not
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* DWORD aligned
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* @xfer_len: Total number of bytes to transfer
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* @xfer_count: Number of bytes transferred so far
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* @start_pkt_count: Packet count at start of transfer
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* @xfer_started: True if the transfer has been started
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* @do_ping: True if a PING request should be issued on this channel
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* @error_state: True if the error count for this transaction is non-zero
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* @halt_on_queue: True if this channel should be halted the next time a
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* request is queued for the channel. This is necessary in
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* slave mode if no request queue space is available when
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* an attempt is made to halt the channel.
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* @halt_pending: True if the host channel has been halted, but the core
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* is not finished flushing queued requests
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* @do_split: Enable split for the channel
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* @complete_split: Enable complete split
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* @hub_addr: Address of high speed hub for the split
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* @hub_port: Port of the low/full speed device for the split
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* @xact_pos: Split transaction position. One of the following values:
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* - DWC2_HCSPLT_XACTPOS_MID
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* - DWC2_HCSPLT_XACTPOS_BEGIN
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* - DWC2_HCSPLT_XACTPOS_END
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* - DWC2_HCSPLT_XACTPOS_ALL
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* @requests: Number of requests issued for this channel since it was
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* assigned to the current transfer (not counting PINGs)
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* @schinfo: Scheduling micro-frame bitmap
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* @ntd: Number of transfer descriptors for the transfer
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* @halt_status: Reason for halting the host channel
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* @hcint: Contents of the HCINT register when the interrupt came
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* @qh: QH for the transfer being processed by this channel
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* @hc_list_entry: For linking to list of host channels
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* @desc_list_addr: Current QH's descriptor list DMA address
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* @desc_list_sz: Current QH's descriptor list size
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* @split_order_list_entry: List entry for keeping track of the order of splits
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*
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* This structure represents the state of a single host channel when acting in
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* host mode. It contains the data items needed to transfer packets to an
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* endpoint via a host channel.
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*/
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struct dwc2_host_chan {
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u8 hc_num;
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unsigned dev_addr:7;
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unsigned ep_num:4;
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unsigned ep_is_in:1;
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unsigned speed:4;
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unsigned ep_type:2;
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unsigned max_packet:11;
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unsigned data_pid_start:2;
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#define DWC2_HC_PID_DATA0 TSIZ_SC_MC_PID_DATA0
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#define DWC2_HC_PID_DATA2 TSIZ_SC_MC_PID_DATA2
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#define DWC2_HC_PID_DATA1 TSIZ_SC_MC_PID_DATA1
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#define DWC2_HC_PID_MDATA TSIZ_SC_MC_PID_MDATA
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#define DWC2_HC_PID_SETUP TSIZ_SC_MC_PID_SETUP
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unsigned multi_count:2;
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u8 *xfer_buf;
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dma_addr_t xfer_dma;
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dma_addr_t align_buf;
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u32 xfer_len;
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u32 xfer_count;
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u16 start_pkt_count;
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u8 xfer_started;
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u8 do_ping;
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u8 error_state;
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u8 halt_on_queue;
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u8 halt_pending;
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u8 do_split;
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u8 complete_split;
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u8 hub_addr;
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u8 hub_port;
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u8 xact_pos;
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#define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID
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#define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END
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#define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN
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#define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL
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u8 requests;
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u8 schinfo;
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u16 ntd;
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enum dwc2_halt_status halt_status;
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u32 hcint;
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struct dwc2_qh *qh;
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struct list_head hc_list_entry;
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dma_addr_t desc_list_addr;
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u32 desc_list_sz;
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struct list_head split_order_list_entry;
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};
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struct dwc2_hcd_pipe_info {
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u8 dev_addr;
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u8 ep_num;
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u8 pipe_type;
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u8 pipe_dir;
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u16 maxp;
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u16 maxp_mult;
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};
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struct dwc2_hcd_iso_packet_desc {
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u32 offset;
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u32 length;
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u32 actual_length;
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u32 status;
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};
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struct dwc2_qtd;
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struct dwc2_hcd_urb {
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void *priv;
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struct dwc2_qtd *qtd;
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void *buf;
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dma_addr_t dma;
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void *setup_packet;
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dma_addr_t setup_dma;
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u32 length;
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u32 actual_length;
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u32 status;
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u32 error_count;
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u32 packet_count;
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u32 flags;
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u16 interval;
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struct dwc2_hcd_pipe_info pipe_info;
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struct dwc2_hcd_iso_packet_desc iso_descs[0];
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};
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/* Phases for control transfers */
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enum dwc2_control_phase {
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DWC2_CONTROL_SETUP,
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DWC2_CONTROL_DATA,
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DWC2_CONTROL_STATUS,
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};
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/* Transaction types */
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enum dwc2_transaction_type {
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DWC2_TRANSACTION_NONE,
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DWC2_TRANSACTION_PERIODIC,
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DWC2_TRANSACTION_NON_PERIODIC,
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DWC2_TRANSACTION_ALL,
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};
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/* The number of elements per LS bitmap (per port on multi_tt) */
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#define DWC2_ELEMENTS_PER_LS_BITMAP DIV_ROUND_UP(DWC2_LS_SCHEDULE_SLICES, \
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BITS_PER_LONG)
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/**
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* struct dwc2_tt - dwc2 data associated with a usb_tt
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*
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* @refcount: Number of Queue Heads (QHs) holding a reference.
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* @usb_tt: Pointer back to the official usb_tt.
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* @periodic_bitmaps: Bitmap for which parts of the 1ms frame are accounted
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* for already. Each is DWC2_ELEMENTS_PER_LS_BITMAP
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* elements (so sizeof(long) times that in bytes).
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*
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* This structure is stored in the hcpriv of the official usb_tt.
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*/
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struct dwc2_tt {
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int refcount;
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struct usb_tt *usb_tt;
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unsigned long periodic_bitmaps[];
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};
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/**
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* struct dwc2_hs_transfer_time - Info about a transfer on the high speed bus.
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*
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* @start_schedule_us: The start time on the main bus schedule. Note that
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* the main bus schedule is tightly packed and this
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* time should be interpreted as tightly packed (so
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* uFrame 0 starts at 0 us, uFrame 1 starts at 100 us
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* instead of 125 us).
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* @duration_us: How long this transfer goes.
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*/
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struct dwc2_hs_transfer_time {
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u32 start_schedule_us;
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u16 duration_us;
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};
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/**
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* struct dwc2_qh - Software queue head structure
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*
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* @hsotg: The HCD state structure for the DWC OTG controller
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* @ep_type: Endpoint type. One of the following values:
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* - USB_ENDPOINT_XFER_CONTROL
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* - USB_ENDPOINT_XFER_BULK
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* - USB_ENDPOINT_XFER_INT
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* - USB_ENDPOINT_XFER_ISOC
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* @ep_is_in: Endpoint direction
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* @maxp: Value from wMaxPacketSize field of Endpoint Descriptor
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* @maxp_mult: Multiplier for maxp
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* @dev_speed: Device speed. One of the following values:
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* - USB_SPEED_LOW
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* - USB_SPEED_FULL
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* - USB_SPEED_HIGH
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* @data_toggle: Determines the PID of the next data packet for
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* non-controltransfers. Ignored for control transfers.
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* One of the following values:
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* - DWC2_HC_PID_DATA0
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* - DWC2_HC_PID_DATA1
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* @ping_state: Ping state
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* @do_split: Full/low speed endpoint on high-speed hub requires split
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* @td_first: Index of first activated isochronous transfer descriptor
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* @td_last: Index of last activated isochronous transfer descriptor
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* @host_us: Bandwidth in microseconds per transfer as seen by host
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* @device_us: Bandwidth in microseconds per transfer as seen by device
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* @host_interval: Interval between transfers as seen by the host. If
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* the host is high speed and the device is low speed this
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* will be 8 times device interval.
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* @device_interval: Interval between transfers as seen by the device.
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* interval.
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* @next_active_frame: (Micro)frame _before_ we next need to put something on
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* the bus. We'll move the qh to active here. If the
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* host is in high speed mode this will be a uframe. If
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* the host is in low speed mode this will be a full frame.
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* @start_active_frame: If we are partway through a split transfer, this will be
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* what next_active_frame was when we started. Otherwise
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* it should always be the same as next_active_frame.
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* @num_hs_transfers: Number of transfers in hs_transfers.
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* Normally this is 1 but can be more than one for splits.
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* Always >= 1 unless the host is in low/full speed mode.
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* @hs_transfers: Transfers that are scheduled as seen by the high speed
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* bus. Not used if host is in low or full speed mode (but
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* note that it IS USED if the device is low or full speed
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* as long as the HOST is in high speed mode).
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* @ls_start_schedule_slice: Start time (in slices) on the low speed bus
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* schedule that's being used by this device. This
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* will be on the periodic_bitmap in a
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* "struct dwc2_tt". Not used if this device is high
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* speed. Note that this is in "schedule slice" which
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* is tightly packed.
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* @ntd: Actual number of transfer descriptors in a list
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* @dw_align_buf: Used instead of original buffer if its physical address
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* is not dword-aligned
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* @dw_align_buf_dma: DMA address for dw_align_buf
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* @qtd_list: List of QTDs for this QH
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* @channel: Host channel currently processing transfers for this QH
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* @qh_list_entry: Entry for QH in either the periodic or non-periodic
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* schedule
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* @desc_list: List of transfer descriptors
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* @desc_list_dma: Physical address of desc_list
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* @desc_list_sz: Size of descriptors list
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* @n_bytes: Xfer Bytes array. Each element corresponds to a transfer
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* descriptor and indicates original XferSize value for the
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* descriptor
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* @unreserve_timer: Timer for releasing periodic reservation.
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* @wait_timer: Timer used to wait before re-queuing.
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* @dwc_tt: Pointer to our tt info (or NULL if no tt).
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* @ttport: Port number within our tt.
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* @tt_buffer_dirty True if clear_tt_buffer_complete is pending
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* @unreserve_pending: True if we planned to unreserve but haven't yet.
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* @schedule_low_speed: True if we have a low/full speed component (either the
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* host is in low/full speed mode or do_split).
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* @want_wait: We should wait before re-queuing; only matters for non-
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* periodic transfers and is ignored for periodic ones.
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* @wait_timer_cancel: Set to true to cancel the wait_timer.
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*
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* @tt_buffer_dirty: True if EP's TT buffer is not clean.
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* A Queue Head (QH) holds the static characteristics of an endpoint and
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* maintains a list of transfers (QTDs) for that endpoint. A QH structure may
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* be entered in either the non-periodic or periodic schedule.
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*/
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struct dwc2_qh {
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struct dwc2_hsotg *hsotg;
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u8 ep_type;
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u8 ep_is_in;
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u16 maxp;
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u16 maxp_mult;
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u8 dev_speed;
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u8 data_toggle;
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u8 ping_state;
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u8 do_split;
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u8 td_first;
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u8 td_last;
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u16 host_us;
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u16 device_us;
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u16 host_interval;
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u16 device_interval;
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u16 next_active_frame;
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u16 start_active_frame;
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s16 num_hs_transfers;
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struct dwc2_hs_transfer_time hs_transfers[DWC2_HS_SCHEDULE_UFRAMES];
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u32 ls_start_schedule_slice;
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u16 ntd;
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u8 *dw_align_buf;
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dma_addr_t dw_align_buf_dma;
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struct list_head qtd_list;
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struct dwc2_host_chan *channel;
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struct list_head qh_list_entry;
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struct dwc2_dma_desc *desc_list;
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dma_addr_t desc_list_dma;
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u32 desc_list_sz;
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u32 *n_bytes;
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struct timer_list unreserve_timer;
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struct hrtimer wait_timer;
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struct dwc2_tt *dwc_tt;
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int ttport;
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unsigned tt_buffer_dirty:1;
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unsigned unreserve_pending:1;
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unsigned schedule_low_speed:1;
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unsigned want_wait:1;
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unsigned wait_timer_cancel:1;
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};
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/**
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* struct dwc2_qtd - Software queue transfer descriptor (QTD)
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*
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* @control_phase: Current phase for control transfers (Setup, Data, or
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* Status)
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* @in_process: Indicates if this QTD is currently processed by HW
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* @data_toggle: Determines the PID of the next data packet for the
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* data phase of control transfers. Ignored for other
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* transfer types. One of the following values:
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* - DWC2_HC_PID_DATA0
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* - DWC2_HC_PID_DATA1
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* @complete_split: Keeps track of the current split type for FS/LS
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* endpoints on a HS Hub
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* @isoc_split_pos: Position of the ISOC split in full/low speed
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* @isoc_frame_index: Index of the next frame descriptor for an isochronous
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* transfer. A frame descriptor describes the buffer
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* position and length of the data to be transferred in the
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* next scheduled (micro)frame of an isochronous transfer.
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* It also holds status for that transaction. The frame
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* index starts at 0.
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* @isoc_split_offset: Position of the ISOC split in the buffer for the
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* current frame
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* @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT
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* @error_count: Holds the number of bus errors that have occurred for
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* a transaction within this transfer
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* @n_desc: Number of DMA descriptors for this QTD
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* @isoc_frame_index_last: Last activated frame (packet) index, used in
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* descriptor DMA mode only
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* @num_naks: Number of NAKs received on this QTD.
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* @urb: URB for this transfer
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* @qh: Queue head for this QTD
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* @qtd_list_entry: For linking to the QH's list of QTDs
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* @isoc_td_first: Index of first activated isochronous transfer
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* descriptor in Descriptor DMA mode
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* @isoc_td_last: Index of last activated isochronous transfer
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* descriptor in Descriptor DMA mode
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*
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* A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
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* interrupt, or isochronous transfer. A single QTD is created for each URB
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* (of one of these types) submitted to the HCD. The transfer associated with
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* a QTD may require one or multiple transactions.
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*
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* A QTD is linked to a Queue Head, which is entered in either the
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* non-periodic or periodic schedule for execution. When a QTD is chosen for
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* execution, some or all of its transactions may be executed. After
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* execution, the state of the QTD is updated. The QTD may be retired if all
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* its transactions are complete or if an error occurred. Otherwise, it
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* remains in the schedule so more transactions can be executed later.
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*/
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struct dwc2_qtd {
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enum dwc2_control_phase control_phase;
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u8 in_process;
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u8 data_toggle;
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u8 complete_split;
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u8 isoc_split_pos;
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u16 isoc_frame_index;
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u16 isoc_split_offset;
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u16 isoc_td_last;
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u16 isoc_td_first;
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u32 ssplit_out_xfer_count;
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u8 error_count;
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u8 n_desc;
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|
u16 isoc_frame_index_last;
|
|
u16 num_naks;
|
|
struct dwc2_hcd_urb *urb;
|
|
struct dwc2_qh *qh;
|
|
struct list_head qtd_list_entry;
|
|
};
|
|
|
|
#ifdef DEBUG
|
|
struct hc_xfer_info {
|
|
struct dwc2_hsotg *hsotg;
|
|
struct dwc2_host_chan *chan;
|
|
};
|
|
#endif
|
|
|
|
u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg);
|
|
|
|
/* Gets the struct usb_hcd that contains a struct dwc2_hsotg */
|
|
static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg)
|
|
{
|
|
return (struct usb_hcd *)hsotg->priv;
|
|
}
|
|
|
|
/*
|
|
* Inline used to disable one channel interrupt. Channel interrupts are
|
|
* disabled when the channel is halted or released by the interrupt handler.
|
|
* There is no need to handle further interrupts of that type until the
|
|
* channel is re-assigned. In fact, subsequent handling may cause crashes
|
|
* because the channel structures are cleaned up when the channel is released.
|
|
*/
|
|
static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr)
|
|
{
|
|
u32 mask = dwc2_readl(hsotg, HCINTMSK(chnum));
|
|
|
|
mask &= ~intr;
|
|
dwc2_writel(hsotg, mask, HCINTMSK(chnum));
|
|
}
|
|
|
|
void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan);
|
|
void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
|
|
enum dwc2_halt_status halt_status);
|
|
void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
|
|
struct dwc2_host_chan *chan);
|
|
|
|
/*
|
|
* Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they
|
|
* are read as 1, they won't clear when written back.
|
|
*/
|
|
static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg)
|
|
{
|
|
u32 hprt0 = dwc2_readl(hsotg, HPRT0);
|
|
|
|
hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG);
|
|
return hprt0;
|
|
}
|
|
|
|
static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe)
|
|
{
|
|
return pipe->ep_num;
|
|
}
|
|
|
|
static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe)
|
|
{
|
|
return pipe->pipe_type;
|
|
}
|
|
|
|
static inline u16 dwc2_hcd_get_maxp(struct dwc2_hcd_pipe_info *pipe)
|
|
{
|
|
return pipe->maxp;
|
|
}
|
|
|
|
static inline u16 dwc2_hcd_get_maxp_mult(struct dwc2_hcd_pipe_info *pipe)
|
|
{
|
|
return pipe->maxp_mult;
|
|
}
|
|
|
|
static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe)
|
|
{
|
|
return pipe->dev_addr;
|
|
}
|
|
|
|
static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe)
|
|
{
|
|
return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC;
|
|
}
|
|
|
|
static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe)
|
|
{
|
|
return pipe->pipe_type == USB_ENDPOINT_XFER_INT;
|
|
}
|
|
|
|
static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe)
|
|
{
|
|
return pipe->pipe_type == USB_ENDPOINT_XFER_BULK;
|
|
}
|
|
|
|
static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe)
|
|
{
|
|
return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL;
|
|
}
|
|
|
|
static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe)
|
|
{
|
|
return pipe->pipe_dir == USB_DIR_IN;
|
|
}
|
|
|
|
static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe)
|
|
{
|
|
return !dwc2_hcd_is_pipe_in(pipe);
|
|
}
|
|
|
|
int dwc2_hcd_init(struct dwc2_hsotg *hsotg);
|
|
void dwc2_hcd_remove(struct dwc2_hsotg *hsotg);
|
|
|
|
/* Transaction Execution Functions */
|
|
enum dwc2_transaction_type dwc2_hcd_select_transactions(
|
|
struct dwc2_hsotg *hsotg);
|
|
void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
|
|
enum dwc2_transaction_type tr_type);
|
|
|
|
/* Schedule Queue Functions */
|
|
/* Implemented in hcd_queue.c */
|
|
struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
|
|
struct dwc2_hcd_urb *urb,
|
|
gfp_t mem_flags);
|
|
void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
|
|
int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
|
|
void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
|
|
void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
|
|
int sched_csplit);
|
|
|
|
void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb);
|
|
int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
|
|
struct dwc2_qh *qh);
|
|
|
|
/* Unlinks and frees a QTD */
|
|
static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg,
|
|
struct dwc2_qtd *qtd,
|
|
struct dwc2_qh *qh)
|
|
{
|
|
list_del(&qtd->qtd_list_entry);
|
|
kfree(qtd);
|
|
qtd = NULL;
|
|
}
|
|
|
|
/* Descriptor DMA support functions */
|
|
void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg,
|
|
struct dwc2_qh *qh);
|
|
void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg,
|
|
struct dwc2_host_chan *chan, int chnum,
|
|
enum dwc2_halt_status halt_status);
|
|
|
|
int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
|
|
gfp_t mem_flags);
|
|
void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
|
|
|
|
/* Check if QH is non-periodic */
|
|
#define dwc2_qh_is_non_per(_qh_ptr_) \
|
|
((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \
|
|
(_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL)
|
|
|
|
#ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC
|
|
static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; }
|
|
static inline bool dbg_qh(struct dwc2_qh *qh) { return true; }
|
|
static inline bool dbg_urb(struct urb *urb) { return true; }
|
|
static inline bool dbg_perio(void) { return true; }
|
|
#else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */
|
|
static inline bool dbg_hc(struct dwc2_host_chan *hc)
|
|
{
|
|
return hc->ep_type == USB_ENDPOINT_XFER_BULK ||
|
|
hc->ep_type == USB_ENDPOINT_XFER_CONTROL;
|
|
}
|
|
|
|
static inline bool dbg_qh(struct dwc2_qh *qh)
|
|
{
|
|
return qh->ep_type == USB_ENDPOINT_XFER_BULK ||
|
|
qh->ep_type == USB_ENDPOINT_XFER_CONTROL;
|
|
}
|
|
|
|
static inline bool dbg_urb(struct urb *urb)
|
|
{
|
|
return usb_pipetype(urb->pipe) == PIPE_BULK ||
|
|
usb_pipetype(urb->pipe) == PIPE_CONTROL;
|
|
}
|
|
|
|
static inline bool dbg_perio(void) { return false; }
|
|
#endif
|
|
|
|
/*
|
|
* Returns true if frame1 index is greater than frame2 index. The comparison
|
|
* is done modulo FRLISTEN_64_SIZE. This accounts for the rollover of the
|
|
* frame number when the max index frame number is reached.
|
|
*/
|
|
static inline bool dwc2_frame_idx_num_gt(u16 fr_idx1, u16 fr_idx2)
|
|
{
|
|
u16 diff = fr_idx1 - fr_idx2;
|
|
u16 sign = diff & (FRLISTEN_64_SIZE >> 1);
|
|
|
|
return diff && !sign;
|
|
}
|
|
|
|
/*
|
|
* Returns true if frame1 is less than or equal to frame2. The comparison is
|
|
* done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the
|
|
* frame number when the max frame number is reached.
|
|
*/
|
|
static inline int dwc2_frame_num_le(u16 frame1, u16 frame2)
|
|
{
|
|
return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1);
|
|
}
|
|
|
|
/*
|
|
* Returns true if frame1 is greater than frame2. The comparison is done
|
|
* modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
|
|
* number when the max frame number is reached.
|
|
*/
|
|
static inline int dwc2_frame_num_gt(u16 frame1, u16 frame2)
|
|
{
|
|
return (frame1 != frame2) &&
|
|
((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1);
|
|
}
|
|
|
|
/*
|
|
* Increments frame by the amount specified by inc. The addition is done
|
|
* modulo HFNUM_MAX_FRNUM. Returns the incremented value.
|
|
*/
|
|
static inline u16 dwc2_frame_num_inc(u16 frame, u16 inc)
|
|
{
|
|
return (frame + inc) & HFNUM_MAX_FRNUM;
|
|
}
|
|
|
|
static inline u16 dwc2_frame_num_dec(u16 frame, u16 dec)
|
|
{
|
|
return (frame + HFNUM_MAX_FRNUM + 1 - dec) & HFNUM_MAX_FRNUM;
|
|
}
|
|
|
|
static inline u16 dwc2_full_frame_num(u16 frame)
|
|
{
|
|
return (frame & HFNUM_MAX_FRNUM) >> 3;
|
|
}
|
|
|
|
static inline u16 dwc2_micro_frame_num(u16 frame)
|
|
{
|
|
return frame & 0x7;
|
|
}
|
|
|
|
/*
|
|
* Returns the Core Interrupt Status register contents, ANDed with the Core
|
|
* Interrupt Mask register contents
|
|
*/
|
|
static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg)
|
|
{
|
|
return dwc2_readl(hsotg, GINTSTS) &
|
|
dwc2_readl(hsotg, GINTMSK);
|
|
}
|
|
|
|
static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb)
|
|
{
|
|
return dwc2_urb->status;
|
|
}
|
|
|
|
static inline u32 dwc2_hcd_urb_get_actual_length(
|
|
struct dwc2_hcd_urb *dwc2_urb)
|
|
{
|
|
return dwc2_urb->actual_length;
|
|
}
|
|
|
|
static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb)
|
|
{
|
|
return dwc2_urb->error_count;
|
|
}
|
|
|
|
static inline void dwc2_hcd_urb_set_iso_desc_params(
|
|
struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset,
|
|
u32 length)
|
|
{
|
|
dwc2_urb->iso_descs[desc_num].offset = offset;
|
|
dwc2_urb->iso_descs[desc_num].length = length;
|
|
}
|
|
|
|
static inline u32 dwc2_hcd_urb_get_iso_desc_status(
|
|
struct dwc2_hcd_urb *dwc2_urb, int desc_num)
|
|
{
|
|
return dwc2_urb->iso_descs[desc_num].status;
|
|
}
|
|
|
|
static inline u32 dwc2_hcd_urb_get_iso_desc_actual_length(
|
|
struct dwc2_hcd_urb *dwc2_urb, int desc_num)
|
|
{
|
|
return dwc2_urb->iso_descs[desc_num].actual_length;
|
|
}
|
|
|
|
static inline int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg,
|
|
struct usb_host_endpoint *ep)
|
|
{
|
|
struct dwc2_qh *qh = ep->hcpriv;
|
|
|
|
if (qh && !list_empty(&qh->qh_list_entry))
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg,
|
|
struct usb_host_endpoint *ep)
|
|
{
|
|
struct dwc2_qh *qh = ep->hcpriv;
|
|
|
|
if (!qh) {
|
|
WARN_ON(1);
|
|
return 0;
|
|
}
|
|
|
|
return qh->host_us;
|
|
}
|
|
|
|
void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
|
|
struct dwc2_host_chan *chan, int chnum,
|
|
struct dwc2_qtd *qtd);
|
|
|
|
/* HCD Core API */
|
|
|
|
/**
|
|
* dwc2_handle_hcd_intr() - Called on every hardware interrupt
|
|
*
|
|
* @hsotg: The DWC2 HCD
|
|
*
|
|
* Returns IRQ_HANDLED if interrupt is handled
|
|
* Return IRQ_NONE if interrupt is not handled
|
|
*/
|
|
irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg);
|
|
|
|
/**
|
|
* dwc2_hcd_stop() - Halts the DWC_otg host mode operation
|
|
*
|
|
* @hsotg: The DWC2 HCD
|
|
*/
|
|
void dwc2_hcd_stop(struct dwc2_hsotg *hsotg);
|
|
|
|
/**
|
|
* dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host,
|
|
* and 0 otherwise
|
|
*
|
|
* @hsotg: The DWC2 HCD
|
|
*/
|
|
int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg);
|
|
|
|
/**
|
|
* dwc2_hcd_dump_state() - Dumps hsotg state
|
|
*
|
|
* @hsotg: The DWC2 HCD
|
|
*
|
|
* NOTE: This function will be removed once the peripheral controller code
|
|
* is integrated and the driver is stable
|
|
*/
|
|
void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg);
|
|
|
|
/* URB interface */
|
|
|
|
/* Transfer flags */
|
|
#define URB_GIVEBACK_ASAP 0x1
|
|
#define URB_SEND_ZERO_PACKET 0x2
|
|
|
|
/* Host driver callbacks */
|
|
struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg,
|
|
void *context, gfp_t mem_flags,
|
|
int *ttport);
|
|
|
|
void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg,
|
|
struct dwc2_tt *dwc_tt);
|
|
int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context);
|
|
void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
|
|
int status);
|
|
|
|
#endif /* __DWC2_HCD_H__ */
|