136 lines
3.9 KiB
C
136 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __DT_BINDINGS_MT6362_H__
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#define __DT_BINDINGS_MT6362_H__
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/* ADC Channel definition */
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#define MT6362_ADCCH_CHGVINDIV5 (0)
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#define MT6362_ADCCH_VSYS (1)
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#define MT6362_ADCCH_VBAT (2)
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#define MT6362_ADCCH_IBUS (3)
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#define MT6362_ADCCH_IBAT (4)
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#define MT6362_ADCCH_RESV5 (5)
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#define MT6362_ADCCH_TEMPJC (6)
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#define MT6362_ADCCH_VREFTS (7)
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#define MT6362_ADCCH_TS (8)
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#define MT6362_ADCCH_PDVBUSDIV10 (9)
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#define MT6362_ADCCH_PDCC1DIV4 (10)
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#define MT6362_ADCCH_PDCC2DIV4 (11)
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#define MT6362_ADCCH_PDSBU1DIV4 (12)
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#define MT6362_ADCCH_PDSBU2DIV4 (13)
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#define MT6362_ADCCH_ZCV (14)
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/* Regulator MODE definitions */
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#define MT6362_REGULATOR_MODE_LP (0)
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#define MT6362_REGULATOR_MODE_NORMAL (1)
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/* IRQ definitions */
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/* 0 ~ 7 */
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#define MT6362_FL_PWR_RDY (0)
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#define MT6362_FL_DETACH (1)
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#define MT6362_FL_RECHG (2)
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#define MT6362_FL_CHG_DONE (3)
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#define MT6362_FL_FL_BK_CHG (4)
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#define MT6362_FL_IEOC (5)
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#define MT6362_FL_CHG_RDY (6)
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#define MT6362_FL_VBUS_GD (7)
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/* 8 ~ 15 */
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#define MT6362_FL_VBUS_OV (8)
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#define MT6362_FL_CHG_BATOV (9)
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#define MT6362_FL_CHG_SYSOV (10)
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#define MT6362_FL_CHG_TOUT (11)
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#define MT6362_FL_CHG_BUSUV (12)
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#define MT6362_FL_CHG_THREG (13)
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#define MT6362_FL_CHG_AICR (14)
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#define MT6362_FL_CHG_MIVR (15)
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/* 16 ~ 23 */
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#define MT6362_FL_SYS_SHORT (16)
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#define MT6362_FL_SYS_MIN (17)
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#define MT6362_FL_AICC_DONE (18)
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#define MT6362_FL_PE_DONE (19)
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#define MT6362_PP_PGB_EVT (21)
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#define MT6362_FT_DIG_THR (22)
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#define MT6362_FL_WDT (23)
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/* 24 ~ 31 */
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#define MT6362_FL_OTG_FAULT (24)
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#define MT6362_FL_OTG_BAT_LBP (25)
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#define MT6362_FL_OTG_CC (26)
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#define MT6362_FL_BC12_HVDCP (30)
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#define MT6362_FL_BC12_DN (31)
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/* 32 ~ 39 */
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#define MT6362_INT_CHRDET_UV (32)
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#define MT6362_INT_CHRDET_OV (33)
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#define MT6362_INT_CHRDET_EXT (34)
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/* 40 ~ 47 */
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#define MT6362_ADC_DONEI (44)
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/* 48 ~ 55 */
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#define MT6362_FLED_STRBPIN_EVT (48)
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#define MT6362_FLED_TORPIN_EVT (49)
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#define MT6362_FLED_TX_EVT (50)
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#define MT6362_FLED_LVF_EVT (51)
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#define MT6362_FLED_LBP_EVT (52)
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#define MT6362_FLED_CHGVINOVP_EVT (53)
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#define MT6362_FLED2_SHORT_EVT (54)
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#define MT6362_FLED1_SHORT_EVT (55)
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/* 56 ~ 63 */
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#define MT6362_FLED2_STRB_EVT (56)
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#define MT6362_FLED1_STRB_EVT (57)
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#define MT6362_FLED2_STRB_TO_EVT (58)
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#define MT6362_FLED1_STRB_TO_EVT (59)
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#define MT6362_FLED2_TOR_EVT (60)
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#define MT6362_FLED1_TOR_EVT (61)
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/* 64 ~ 71 */
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#define MT6362_APWDTRST_EVT (65)
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#define MT6362_EN_EVT (66)
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#define MT6362_QONB_RST_EVT (67)
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#define MT6362_MRSTB_EVT (68)
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#define MT6362_VDDAOV_EVT (70)
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#define MT6362_SYSUV_EVT (71)
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/* 72 ~ 79 */
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#define MT6362_OTP0_EVT (72)
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#define MT6362_OTP1_EVT (73)
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#define MT6362_OTP2_EVT (74)
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#define MT6362_OTP3_EVT (75)
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#define MT6362_OTP4_EVT (76)
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#define MT6362_OTP5_EVT (77)
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/* 80 ~ 87 */
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#define MT6362_BUCK1_OC_SDN_EVT (81)
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#define MT6362_BUCK2_OC_SDN_EVT (82)
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#define MT6362_BUCK3_OC_SDN_EVT (83)
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#define MT6362_BUCK4_OC_SDN_EVT (84)
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#define MT6362_BUCK5_OC_SDN_EVT (85)
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#define MT6362_BUCK6_OC_SDN_EVT (86)
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/* 88 ~ 95 */
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#define MT6362_BUCK1_PGB_EVT (89)
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#define MT6362_BUCK2_PGB_EVT (90)
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#define MT6362_BUCK3_PGB_EVT (91)
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#define MT6362_BUCK4_PGB_EVT (92)
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#define MT6362_BUCK5_PGB_EVT (93)
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#define MT6362_BUCK6_PGB_EVT (94)
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/* 96 ~ 103 */
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#define MT6362_LDO1_OC_EVT (97)
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#define MT6362_LDO2_OC_EVT (98)
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#define MT6362_LDO3_OC_EVT (99)
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#define MT6362_LDO4_OC_EVT (100)
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#define MT6362_LDO5_OC_EVT (101)
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#define MT6362_LDO6_OC_EVT (102)
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#define MT6362_LDO7_OC_EVT (103)
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/* 104 ~ 111 */
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#define MT6362_VDIG18_PGB_EVT (104)
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#define MT6362_LDO1_PGB_EVT (105)
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#define MT6362_LDO2_PGB_EVT (106)
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#define MT6362_LDO3_PGB_EVT (107)
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#define MT6362_LDO4_PGB_EVT (108)
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#define MT6362_LDO5_PGB_EVT (109)
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#define MT6362_LDO6_PGB_EVT (110)
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#define MT6362_LDO7_PGB_EVT (111)
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/* 112 ~ 119 */
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#define MT6362_USBID_EVT (112)
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/* 120 ~ 127 */
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#define MT6362_PD_EVT (120)
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#endif /* __DT_BINDINGS_MT6362_H__ */
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