555 lines
15 KiB
C
555 lines
15 KiB
C
/*
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* VGICv2 MMIO handling functions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/irqchip/arm-gic.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <linux/nospec.h>
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#include <kvm/iodev.h>
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#include <kvm/arm_vgic.h>
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#include "vgic.h"
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#include "vgic-mmio.h"
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/*
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* The Revision field in the IIDR have the following meanings:
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*
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* Revision 1: Report GICv2 interrupts as group 0 instead of group 1
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* Revision 2: Interrupt groups are guest-configurable and signaled using
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* their configured groups.
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*/
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static unsigned long vgic_mmio_read_v2_misc(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
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u32 value;
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switch (addr & 0x0c) {
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case GIC_DIST_CTRL:
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value = vgic->enabled ? GICD_ENABLE : 0;
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break;
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case GIC_DIST_CTR:
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value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS;
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value = (value >> 5) - 1;
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value |= (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
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break;
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case GIC_DIST_IIDR:
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value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) |
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(vgic->implementation_rev << GICD_IIDR_REVISION_SHIFT) |
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(IMPLEMENTER_ARM << GICD_IIDR_IMPLEMENTER_SHIFT);
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break;
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default:
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return 0;
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}
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return value;
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}
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static void vgic_mmio_write_v2_misc(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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bool was_enabled = dist->enabled;
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switch (addr & 0x0c) {
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case GIC_DIST_CTRL:
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dist->enabled = val & GICD_ENABLE;
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if (!was_enabled && dist->enabled)
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vgic_kick_vcpus(vcpu->kvm);
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break;
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case GIC_DIST_CTR:
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case GIC_DIST_IIDR:
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/* Nothing to do */
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return;
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}
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}
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static int vgic_mmio_uaccess_write_v2_misc(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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switch (addr & 0x0c) {
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case GIC_DIST_IIDR:
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if (val != vgic_mmio_read_v2_misc(vcpu, addr, len))
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return -EINVAL;
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/*
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* If we observe a write to GICD_IIDR we know that userspace
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* has been updated and has had a chance to cope with older
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* kernels (VGICv2 IIDR.Revision == 0) incorrectly reporting
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* interrupts as group 1, and therefore we now allow groups to
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* be user writable. Doing this by default would break
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* migration from old kernels to new kernels with legacy
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* userspace.
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*/
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vcpu->kvm->arch.vgic.v2_groups_user_writable = true;
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return 0;
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}
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vgic_mmio_write_v2_misc(vcpu, addr, len, val);
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return 0;
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}
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static int vgic_mmio_uaccess_write_v2_group(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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if (vcpu->kvm->arch.vgic.v2_groups_user_writable)
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vgic_mmio_write_group(vcpu, addr, len, val);
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return 0;
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}
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static void vgic_mmio_write_sgir(struct kvm_vcpu *source_vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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int nr_vcpus = atomic_read(&source_vcpu->kvm->online_vcpus);
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int intid = val & 0xf;
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int targets = (val >> 16) & 0xff;
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int mode = (val >> 24) & 0x03;
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int c;
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struct kvm_vcpu *vcpu;
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unsigned long flags;
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switch (mode) {
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case 0x0: /* as specified by targets */
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break;
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case 0x1:
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targets = (1U << nr_vcpus) - 1; /* all, ... */
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targets &= ~(1U << source_vcpu->vcpu_id); /* but self */
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break;
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case 0x2: /* this very vCPU only */
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targets = (1U << source_vcpu->vcpu_id);
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break;
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case 0x3: /* reserved */
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return;
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}
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kvm_for_each_vcpu(c, vcpu, source_vcpu->kvm) {
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struct vgic_irq *irq;
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if (!(targets & (1U << c)))
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continue;
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irq = vgic_get_irq(source_vcpu->kvm, vcpu, intid);
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spin_lock_irqsave(&irq->irq_lock, flags);
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irq->pending_latch = true;
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irq->source |= 1U << source_vcpu->vcpu_id;
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vgic_queue_irq_unlock(source_vcpu->kvm, irq, flags);
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vgic_put_irq(source_vcpu->kvm, irq);
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}
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}
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static unsigned long vgic_mmio_read_target(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
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int i;
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u64 val = 0;
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for (i = 0; i < len; i++) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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val |= (u64)irq->targets << (i * 8);
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vgic_put_irq(vcpu->kvm, irq);
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}
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return val;
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}
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static void vgic_mmio_write_target(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
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u8 cpu_mask = GENMASK(atomic_read(&vcpu->kvm->online_vcpus) - 1, 0);
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int i;
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unsigned long flags;
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/* GICD_ITARGETSR[0-7] are read-only */
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if (intid < VGIC_NR_PRIVATE_IRQS)
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return;
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for (i = 0; i < len; i++) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid + i);
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int target;
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spin_lock_irqsave(&irq->irq_lock, flags);
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irq->targets = (val >> (i * 8)) & cpu_mask;
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target = irq->targets ? __ffs(irq->targets) : 0;
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irq->target_vcpu = kvm_get_vcpu(vcpu->kvm, target);
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spin_unlock_irqrestore(&irq->irq_lock, flags);
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vgic_put_irq(vcpu->kvm, irq);
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}
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}
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static unsigned long vgic_mmio_read_sgipend(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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u32 intid = addr & 0x0f;
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int i;
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u64 val = 0;
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for (i = 0; i < len; i++) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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val |= (u64)irq->source << (i * 8);
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vgic_put_irq(vcpu->kvm, irq);
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}
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return val;
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}
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static void vgic_mmio_write_sgipendc(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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u32 intid = addr & 0x0f;
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int i;
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unsigned long flags;
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for (i = 0; i < len; i++) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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spin_lock_irqsave(&irq->irq_lock, flags);
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irq->source &= ~((val >> (i * 8)) & 0xff);
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if (!irq->source)
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irq->pending_latch = false;
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spin_unlock_irqrestore(&irq->irq_lock, flags);
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vgic_put_irq(vcpu->kvm, irq);
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}
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}
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static void vgic_mmio_write_sgipends(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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u32 intid = addr & 0x0f;
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int i;
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unsigned long flags;
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for (i = 0; i < len; i++) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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spin_lock_irqsave(&irq->irq_lock, flags);
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irq->source |= (val >> (i * 8)) & 0xff;
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if (irq->source) {
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irq->pending_latch = true;
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vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
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} else {
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spin_unlock_irqrestore(&irq->irq_lock, flags);
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}
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vgic_put_irq(vcpu->kvm, irq);
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}
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}
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#define GICC_ARCH_VERSION_V2 0x2
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/* These are for userland accesses only, there is no guest-facing emulation. */
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static unsigned long vgic_mmio_read_vcpuif(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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struct vgic_vmcr vmcr;
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u32 val;
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vgic_get_vmcr(vcpu, &vmcr);
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switch (addr & 0xff) {
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case GIC_CPU_CTRL:
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val = vmcr.grpen0 << GIC_CPU_CTRL_EnableGrp0_SHIFT;
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val |= vmcr.grpen1 << GIC_CPU_CTRL_EnableGrp1_SHIFT;
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val |= vmcr.ackctl << GIC_CPU_CTRL_AckCtl_SHIFT;
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val |= vmcr.fiqen << GIC_CPU_CTRL_FIQEn_SHIFT;
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val |= vmcr.cbpr << GIC_CPU_CTRL_CBPR_SHIFT;
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val |= vmcr.eoim << GIC_CPU_CTRL_EOImodeNS_SHIFT;
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break;
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case GIC_CPU_PRIMASK:
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/*
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* Our KVM_DEV_TYPE_ARM_VGIC_V2 device ABI exports the
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* the PMR field as GICH_VMCR.VMPriMask rather than
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* GICC_PMR.Priority, so we expose the upper five bits of
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* priority mask to userspace using the lower bits in the
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* unsigned long.
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*/
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val = (vmcr.pmr & GICV_PMR_PRIORITY_MASK) >>
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GICV_PMR_PRIORITY_SHIFT;
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break;
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case GIC_CPU_BINPOINT:
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val = vmcr.bpr;
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break;
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case GIC_CPU_ALIAS_BINPOINT:
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val = vmcr.abpr;
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break;
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case GIC_CPU_IDENT:
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val = ((PRODUCT_ID_KVM << 20) |
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(GICC_ARCH_VERSION_V2 << 16) |
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IMPLEMENTER_ARM);
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break;
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default:
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return 0;
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}
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return val;
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}
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static void vgic_mmio_write_vcpuif(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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struct vgic_vmcr vmcr;
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vgic_get_vmcr(vcpu, &vmcr);
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switch (addr & 0xff) {
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case GIC_CPU_CTRL:
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vmcr.grpen0 = !!(val & GIC_CPU_CTRL_EnableGrp0);
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vmcr.grpen1 = !!(val & GIC_CPU_CTRL_EnableGrp1);
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vmcr.ackctl = !!(val & GIC_CPU_CTRL_AckCtl);
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vmcr.fiqen = !!(val & GIC_CPU_CTRL_FIQEn);
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vmcr.cbpr = !!(val & GIC_CPU_CTRL_CBPR);
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vmcr.eoim = !!(val & GIC_CPU_CTRL_EOImodeNS);
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break;
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case GIC_CPU_PRIMASK:
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/*
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* Our KVM_DEV_TYPE_ARM_VGIC_V2 device ABI exports the
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* the PMR field as GICH_VMCR.VMPriMask rather than
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* GICC_PMR.Priority, so we expose the upper five bits of
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* priority mask to userspace using the lower bits in the
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* unsigned long.
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*/
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vmcr.pmr = (val << GICV_PMR_PRIORITY_SHIFT) &
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GICV_PMR_PRIORITY_MASK;
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break;
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case GIC_CPU_BINPOINT:
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vmcr.bpr = val;
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break;
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case GIC_CPU_ALIAS_BINPOINT:
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vmcr.abpr = val;
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break;
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}
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vgic_set_vmcr(vcpu, &vmcr);
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}
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static unsigned long vgic_mmio_read_apr(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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int n; /* which APRn is this */
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n = (addr >> 2) & 0x3;
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if (kvm_vgic_global_state.type == VGIC_V2) {
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/* GICv2 hardware systems support max. 32 groups */
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if (n != 0)
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return 0;
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return vcpu->arch.vgic_cpu.vgic_v2.vgic_apr;
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} else {
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struct vgic_v3_cpu_if *vgicv3 = &vcpu->arch.vgic_cpu.vgic_v3;
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if (n > vgic_v3_max_apr_idx(vcpu))
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return 0;
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n = array_index_nospec(n, 4);
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/* GICv3 only uses ICH_AP1Rn for memory mapped (GICv2) guests */
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return vgicv3->vgic_ap1r[n];
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}
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}
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static void vgic_mmio_write_apr(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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int n; /* which APRn is this */
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n = (addr >> 2) & 0x3;
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if (kvm_vgic_global_state.type == VGIC_V2) {
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/* GICv2 hardware systems support max. 32 groups */
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if (n != 0)
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return;
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vcpu->arch.vgic_cpu.vgic_v2.vgic_apr = val;
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} else {
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struct vgic_v3_cpu_if *vgicv3 = &vcpu->arch.vgic_cpu.vgic_v3;
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if (n > vgic_v3_max_apr_idx(vcpu))
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return;
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n = array_index_nospec(n, 4);
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/* GICv3 only uses ICH_AP1Rn for memory mapped (GICv2) guests */
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vgicv3->vgic_ap1r[n] = val;
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}
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}
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static const struct vgic_register_region vgic_v2_dist_registers[] = {
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REGISTER_DESC_WITH_LENGTH_UACCESS(GIC_DIST_CTRL,
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vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc,
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NULL, vgic_mmio_uaccess_write_v2_misc,
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12, VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_IGROUP,
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vgic_mmio_read_group, vgic_mmio_write_group,
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NULL, vgic_mmio_uaccess_write_v2_group, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_SET,
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vgic_mmio_read_enable, vgic_mmio_write_senable, NULL, NULL, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_CLEAR,
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vgic_mmio_read_enable, vgic_mmio_write_cenable, NULL, NULL, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_SET,
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vgic_mmio_read_pending, vgic_mmio_write_spending, NULL, NULL, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_CLEAR,
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vgic_mmio_read_pending, vgic_mmio_write_cpending, NULL, NULL, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_SET,
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vgic_mmio_read_active, vgic_mmio_write_sactive,
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NULL, vgic_mmio_uaccess_write_sactive, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_CLEAR,
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vgic_mmio_read_active, vgic_mmio_write_cactive,
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NULL, vgic_mmio_uaccess_write_cactive, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PRI,
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vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL,
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8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_TARGET,
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vgic_mmio_read_target, vgic_mmio_write_target, NULL, NULL, 8,
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VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_CONFIG,
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vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GIC_DIST_SOFTINT,
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vgic_mmio_read_raz, vgic_mmio_write_sgir, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_CLEAR,
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vgic_mmio_read_sgipend, vgic_mmio_write_sgipendc, 16,
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VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_SET,
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vgic_mmio_read_sgipend, vgic_mmio_write_sgipends, 16,
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VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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};
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static const struct vgic_register_region vgic_v2_cpu_registers[] = {
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REGISTER_DESC_WITH_LENGTH(GIC_CPU_CTRL,
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vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GIC_CPU_PRIMASK,
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vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GIC_CPU_BINPOINT,
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vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GIC_CPU_ALIAS_BINPOINT,
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vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GIC_CPU_ACTIVEPRIO,
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vgic_mmio_read_apr, vgic_mmio_write_apr, 16,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GIC_CPU_IDENT,
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vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
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VGIC_ACCESS_32bit),
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};
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unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev)
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{
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dev->regions = vgic_v2_dist_registers;
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dev->nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
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kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
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return SZ_4K;
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}
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int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
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{
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const struct vgic_register_region *region;
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struct vgic_io_device iodev;
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struct vgic_reg_attr reg_attr;
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struct kvm_vcpu *vcpu;
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gpa_t addr;
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int ret;
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ret = vgic_v2_parse_attr(dev, attr, ®_attr);
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if (ret)
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return ret;
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vcpu = reg_attr.vcpu;
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addr = reg_attr.addr;
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switch (attr->group) {
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case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
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iodev.regions = vgic_v2_dist_registers;
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iodev.nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
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iodev.base_addr = 0;
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break;
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case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
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iodev.regions = vgic_v2_cpu_registers;
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iodev.nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers);
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iodev.base_addr = 0;
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break;
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default:
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return -ENXIO;
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}
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/* We only support aligned 32-bit accesses. */
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if (addr & 3)
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return -ENXIO;
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region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32));
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if (!region)
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return -ENXIO;
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return 0;
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}
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int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
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int offset, u32 *val)
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{
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struct vgic_io_device dev = {
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.regions = vgic_v2_cpu_registers,
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.nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers),
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.iodev_type = IODEV_CPUIF,
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};
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return vgic_uaccess(vcpu, &dev, is_write, offset, val);
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}
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int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
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int offset, u32 *val)
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{
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struct vgic_io_device dev = {
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.regions = vgic_v2_dist_registers,
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.nr_regions = ARRAY_SIZE(vgic_v2_dist_registers),
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.iodev_type = IODEV_DIST,
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};
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return vgic_uaccess(vcpu, &dev, is_write, offset, val);
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}
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