104 lines
3.4 KiB
Plaintext
104 lines
3.4 KiB
Plaintext
* Samsung Audio Subsystem Clock Controller
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The Samsung Audio Subsystem clock controller generates and supplies clocks
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to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
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binding described here is applicable to all SoCs in Exynos family.
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Required Properties:
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- compatible: should be one of the following:
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- "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
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- "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
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SoCs.
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- "samsung,exynos5410-audss-clock" - controller compatible with Exynos5410
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SoCs.
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- "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
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SoCs.
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- reg: physical base address and length of the controller's register set.
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- #clock-cells: should be 1.
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- clocks:
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- pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll"
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is used if not specified.
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- pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll"
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is used if not specified.
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- cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not
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specified.
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- sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if
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not specified.
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- sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not
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specified.
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- clock-names: Aliases for the above clocks. They should be "pll_ref",
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"pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively.
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Optional Properties:
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- power-domains: a phandle to respective power domain node as described by
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generic PM domain bindings (see power/power_domain.txt for more
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information).
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The following is the list of clocks generated by the controller. Each clock is
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assigned an identifier and client nodes use this identifier to specify the
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clock which they consume. Some of the clocks are available only on a particular
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Exynos4 SoC and this is specified where applicable.
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Provided clocks:
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Clock ID SoC (if specific)
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-----------------------------------------------
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mout_audss 0
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mout_i2s 1
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dout_srp 2
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dout_aud_bus 3
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dout_i2s 4
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srp_clk 5
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i2s_bus 6
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sclk_i2s 7
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pcm_bus 8
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sclk_pcm 9
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adma 10 Exynos5420
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Example 1: An example of a clock controller node using the default input
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clock names is listed below.
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clock_audss: audss-clock-controller@3810000 {
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compatible = "samsung,exynos5250-audss-clock";
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reg = <0x03810000 0x0C>;
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#clock-cells = <1>;
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};
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Example 2: An example of a clock controller node with the input clocks
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specified.
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clock_audss: audss-clock-controller@3810000 {
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compatible = "samsung,exynos5250-audss-clock";
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reg = <0x03810000 0x0C>;
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#clock-cells = <1>;
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clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>,
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<&ext_i2s_clk>;
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clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
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};
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Example 3: I2S controller node that consumes the clock generated by the clock
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controller. Refer to the standard clock bindings for information
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about 'clocks' and 'clock-names' property.
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i2s0: i2s@3830000 {
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compatible = "samsung,i2s-v5";
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reg = <0x03830000 0x100>;
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dmas = <&pdma0 10
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&pdma0 9
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&pdma0 8>;
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dma-names = "tx", "rx", "tx-sec";
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clocks = <&clock_audss EXYNOS_I2S_BUS>,
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<&clock_audss EXYNOS_I2S_BUS>,
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<&clock_audss EXYNOS_SCLK_I2S>,
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<&clock_audss EXYNOS_MOUT_AUDSS>,
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<&clock_audss EXYNOS_MOUT_I2S>;
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clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
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"mout_audss", "mout_i2s";
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};
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