239 lines
8.1 KiB
Plaintext
239 lines
8.1 KiB
Plaintext
* Texas Instruments Keystone Navigator Queue Management SubSystem driver
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The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of
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the main hardware sub system which forms the backbone of the Keystone
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multi-core Navigator. QMSS consist of queue managers, packed-data structure
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processors(PDSP), linking RAM, descriptor pools and infrastructure
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Packet DMA.
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The Queue Manager is a hardware module that is responsible for accelerating
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management of the packet queues. Packets are queued/de-queued by writing or
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reading descriptor address to a particular memory mapped location. The PDSPs
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perform QMSS related functions like accumulation, QoS, or event management.
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Linking RAM registers are used to link the descriptors which are stored in
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descriptor RAM. Descriptor RAM is configurable as internal or external memory.
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The QMSS driver manages the PDSP setups, linking RAM regions,
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queue pool management (allocation, push, pop and notify) and descriptor
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pool management.
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Required properties:
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- compatible : Must be "ti,keystone-navigator-qmss".
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: Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
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- clocks : phandle to the reference clock for this device.
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- queue-range : <start number> total range of queue numbers for the device.
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- linkram0 : <address size> for internal link ram, where size is the total
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link ram entries.
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- linkram1 : <address size> for external link ram, where size is the total
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external link ram entries. If the address is specified as "0"
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driver will allocate memory.
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- qmgrs : child node describing the individual queue managers on the
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SoC. On keystone 1 devices there should be only one node.
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On keystone 2 devices there can be more than 1 node.
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-- managed-queues : the actual queues managed by each queue manager
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instance, specified as <"base queue #" "# of queues">.
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-- reg : Address and size of the register set for the device.
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Register regions should be specified in the following
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order
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- Queue Peek region.
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- Queue status RAM.
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- Queue configuration region.
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- Descriptor memory setup region.
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- Queue Management/Queue Proxy region for queue Push.
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- Queue Management/Queue Proxy region for queue Pop.
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For QMSS on K2G SoC, following QM reg indexes are used in that order
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- Queue Peek region.
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- Queue configuration region.
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- Queue Management/Queue Proxy region for queue Push/Pop.
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- queue-pools : child node classifying the queue ranges into pools.
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Queue ranges are grouped into 3 type of pools:
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- qpend : pool of qpend(interruptible) queues
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- general-purpose : pool of general queues, primarily used
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as free descriptor queues or the
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transmit DMA queues.
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- accumulator : pool of queues on PDSP accumulator channel
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Each range can have the following properties:
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-- qrange : number of queues to use per queue range, specified as
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<"base queue #" "# of queues">.
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-- interrupts : Optional property to specify the interrupt mapping
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for interruptible queues. The driver additionally sets
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the interrupt affinity hint based on the cpu mask.
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-- qalloc-by-id : Optional property to specify that the queues in this
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range can only be allocated by queue id.
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-- accumulator : Accumulator channel specification. Any of the PDSPs in
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QMSS can be loaded with the accumulator firmware. The
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accumulator firmware’s job is to poll a select number of
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queues looking for descriptors that have been pushed
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into them. Descriptors are popped from the queue and
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placed in a buffer provided by the host. When the list
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becomes full or a programmed time period expires, the
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accumulator triggers an interrupt to the host to read
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the buffer for descriptor information. This firmware
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comes in 16, 32, and 48 channel builds. Each of these
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channels can be configured to monitor 32 contiguous
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queues. Accumulator channel property is specified as:
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<pdsp-id, channel, entries, pacing mode, latency>
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pdsp-id : QMSS PDSP running accumulator firmware
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on which the channel has to be
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configured
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channel : Accumulator channel number
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entries : Size of the accumulator descriptor list
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pacing mode : Interrupt pacing mode
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0 : None, i.e interrupt on list full only
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1 : Time delay since last interrupt
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2 : Time delay since first new packet
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3 : Time delay since last new packet
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latency : time to delay the interrupt, specified
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in microseconds.
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-- multi-queue : Optional property to specify that the channel has to
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monitor up to 32 queues starting at the base queue #.
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- descriptor-regions : child node describing the memory regions for keystone
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navigator packet DMA descriptors. The memory for
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descriptors will be allocated by the driver.
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-- id : region number in QMSS.
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-- region-spec : specifies the number of descriptors in the
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region, specified as
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<"# of descriptors" "descriptor size">.
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-- link-index : start index, i.e. index of the first
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descriptor in the region.
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Optional properties:
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- dma-coherent : Present if DMA operations are coherent.
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- pdsps : child node describing the PDSP configuration.
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-- firmware : firmware to be loaded on the PDSP.
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-- id : the qmss pdsp that will run the firmware.
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-- reg : Address and size of the register set for the PDSP.
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Register regions should be specified in the following
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order
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- PDSP internal RAM region.
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- PDSP control/status region registers.
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- QMSS interrupt distributor registers.
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- PDSP command interface region.
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Example:
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qmss: qmss@2a40000 {
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compatible = "ti,keystone-qmss";
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dma-coherent;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&chipclk13>;
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ranges;
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queue-range = <0 0x4000>;
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linkram0 = <0x100000 0x8000>;
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linkram1 = <0x0 0x10000>;
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qmgrs {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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qmgr0 {
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managed-queues = <0 0x2000>;
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reg = <0x2a40000 0x20000>,
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<0x2a06000 0x400>,
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<0x2a02000 0x1000>,
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<0x2a03000 0x1000>,
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<0x23a80000 0x20000>,
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<0x2a80000 0x20000>;
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};
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qmgr1 {
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managed-queues = <0x2000 0x2000>;
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reg = <0x2a60000 0x20000>,
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<0x2a06400 0x400>,
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<0x2a04000 0x1000>,
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<0x2a05000 0x1000>,
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<0x23aa0000 0x20000>,
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<0x2aa0000 0x20000>;
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};
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};
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queue-pools {
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qpend {
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qpend-0 {
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qrange = <658 8>;
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interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
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0 43 0xf04 0 44 0xf04 0 45 0xf04
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0 46 0xf04 0 47 0xf04>;
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};
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qpend-1 {
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qrange = <8704 16>;
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interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
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0 51 0xf04 0 52 0xf04 0 53 0xf04
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0 54 0xf04 0 55 0xf04 0 56 0xf04
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0 57 0xf04 0 58 0xf04 0 59 0xf04
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0 60 0xf04 0 61 0xf04 0 62 0xf04
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0 63 0xf04>;
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qalloc-by-id;
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};
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qpend-2 {
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qrange = <8720 16>;
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interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
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0 59 0xf04 0 68 0xf04 0 69 0xf04
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0 70 0xf04 0 71 0xf04 0 72 0xf04
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0 73 0xf04 0 74 0xf04 0 75 0xf04
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0 76 0xf04 0 77 0xf04 0 78 0xf04
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0 79 0xf04>;
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};
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};
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general-purpose {
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gp-0 {
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qrange = <4000 64>;
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};
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netcp-tx {
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qrange = <640 9>;
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qalloc-by-id;
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};
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};
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accumulator {
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acc-0 {
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qrange = <128 32>;
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accumulator = <0 36 16 2 50>;
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interrupts = <0 215 0xf01>;
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multi-queue;
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qalloc-by-id;
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};
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acc-1 {
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qrange = <160 32>;
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accumulator = <0 37 16 2 50>;
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interrupts = <0 216 0xf01>;
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multi-queue;
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};
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acc-2 {
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qrange = <192 32>;
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accumulator = <0 38 16 2 50>;
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interrupts = <0 217 0xf01>;
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multi-queue;
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};
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acc-3 {
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qrange = <224 32>;
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accumulator = <0 39 16 2 50>;
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interrupts = <0 218 0xf01>;
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multi-queue;
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};
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};
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};
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descriptor-regions {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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region-12 {
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id = <12>;
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region-spec = <8192 128>; /* num_desc desc_size */
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link-index = <0x4000>;
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};
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};
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pdsps {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pdsp0@2a10000 {
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reg = <0x2a10000 0x1000>,
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<0x2a0f000 0x100>,
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<0x2a0c000 0x3c8>,
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<0x2a20000 0x4000>;
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id = <0>;
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};
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};
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}; /* qmss */
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