126 lines
3.7 KiB
C
126 lines
3.7 KiB
C
/*
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* Linux/PA-RISC Project (http://www.parisc-linux.org/)
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*
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* Floating-point emulation code
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* Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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* linux/arch/math-emu/driver.c.c
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*
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* decodes and dispatches unimplemented FPU instructions
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*
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* Copyright (C) 1999, 2000 Philipp Rumpf <prumpf@tux.org>
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* Copyright (C) 2001 Hewlett-Packard <bame@debian.org>
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*/
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#include <linux/sched/signal.h>
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#include "float.h"
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#include "math-emu.h"
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#define fptpos 31
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#define fpr1pos 10
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#define extru(r,pos,len) (((r) >> (31-(pos))) & (( 1 << (len)) - 1))
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#define FPUDEBUG 0
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/* Format of the floating-point exception registers. */
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struct exc_reg {
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unsigned int exception : 6;
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unsigned int ei : 26;
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};
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/* Macros for grabbing bits of the instruction format from the 'ei'
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field above. */
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/* Major opcode 0c and 0e */
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#define FP0CE_UID(i) (((i) >> 6) & 3)
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#define FP0CE_CLASS(i) (((i) >> 9) & 3)
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#define FP0CE_SUBOP(i) (((i) >> 13) & 7)
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#define FP0CE_SUBOP1(i) (((i) >> 15) & 7) /* Class 1 subopcode */
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#define FP0C_FORMAT(i) (((i) >> 11) & 3)
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#define FP0E_FORMAT(i) (((i) >> 11) & 1)
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/* Major opcode 0c, uid 2 (performance monitoring) */
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#define FPPM_SUBOP(i) (((i) >> 9) & 0x1f)
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/* Major opcode 2e (fused operations). */
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#define FP2E_SUBOP(i) (((i) >> 5) & 1)
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#define FP2E_FORMAT(i) (((i) >> 11) & 1)
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/* Major opcode 26 (FMPYSUB) */
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/* Major opcode 06 (FMPYADD) */
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#define FPx6_FORMAT(i) ((i) & 0x1f)
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/* Flags and enable bits of the status word. */
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#define FPSW_FLAGS(w) ((w) >> 27)
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#define FPSW_ENABLE(w) ((w) & 0x1f)
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#define FPSW_V (1<<4)
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#define FPSW_Z (1<<3)
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#define FPSW_O (1<<2)
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#define FPSW_U (1<<1)
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#define FPSW_I (1<<0)
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/* Handle a floating point exception. Return zero if the faulting
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instruction can be completed successfully. */
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int
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handle_fpe(struct pt_regs *regs)
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{
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extern void printbinary(unsigned long x, int nbits);
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unsigned int orig_sw, sw;
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int signalcode;
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/* need an intermediate copy of float regs because FPU emulation
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* code expects an artificial last entry which contains zero
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*
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* also, the passed in fr registers contain one word that defines
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* the fpu type. the fpu type information is constructed
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* inside the emulation code
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*/
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__u64 frcopy[36];
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memcpy(frcopy, regs->fr, sizeof regs->fr);
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frcopy[32] = 0;
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memcpy(&orig_sw, frcopy, sizeof(orig_sw));
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if (FPUDEBUG) {
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printk(KERN_DEBUG "FP VZOUICxxxxCQCQCQCQCQCRMxxTDVZOUI ->\n ");
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printbinary(orig_sw, 32);
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printk(KERN_DEBUG "\n");
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}
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signalcode = decode_fpu(frcopy, 0x666);
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/* Status word = FR0L. */
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memcpy(&sw, frcopy, sizeof(sw));
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if (FPUDEBUG) {
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printk(KERN_DEBUG "VZOUICxxxxCQCQCQCQCQCRMxxTDVZOUI decode_fpu returns %d|0x%x\n",
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signalcode >> 24, signalcode & 0xffffff);
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printbinary(sw, 32);
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printk(KERN_DEBUG "\n");
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}
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memcpy(regs->fr, frcopy, sizeof regs->fr);
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if (signalcode != 0) {
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force_sig_fault(signalcode >> 24, signalcode & 0xffffff,
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(void __user *) regs->iaoq[0], current);
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return -1;
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}
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return signalcode ? -1 : 0;
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}
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