64 lines
1.6 KiB
C
64 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_PAGE_32_H
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#define _ASM_POWERPC_PAGE_32_H
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#include <asm/cache.h>
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#if defined(CONFIG_PHYSICAL_ALIGN) && (CONFIG_PHYSICAL_START != 0)
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#if (CONFIG_PHYSICAL_START % CONFIG_PHYSICAL_ALIGN) != 0
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#error "CONFIG_PHYSICAL_START must be a multiple of CONFIG_PHYSICAL_ALIGN"
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#endif
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#endif
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#define VM_DATA_DEFAULT_FLAGS VM_DATA_DEFAULT_FLAGS32
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#ifdef CONFIG_NOT_COHERENT_CACHE
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#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
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#endif
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#ifdef CONFIG_PTE_64BIT
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#define PTE_FLAGS_OFFSET 4 /* offset of PTE flags, in bytes */
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#else
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#define PTE_FLAGS_OFFSET 0
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#endif
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#ifdef CONFIG_PPC_256K_PAGES
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#define PTE_SHIFT (PAGE_SHIFT - PTE_T_LOG2 - 2) /* 1/4 of a page */
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#else
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#define PTE_SHIFT (PAGE_SHIFT - PTE_T_LOG2) /* full page */
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#endif
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#ifndef __ASSEMBLY__
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/*
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* The basic type of a PTE - 64 bits for those CPUs with > 32 bit
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* physical addressing.
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*/
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#ifdef CONFIG_PTE_64BIT
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typedef unsigned long long pte_basic_t;
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#else
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typedef unsigned long pte_basic_t;
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#endif
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/*
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* Clear page using the dcbz instruction, which doesn't cause any
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* memory traffic (except to write out any cache lines which get
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* displaced). This only works on cacheable memory.
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*/
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static inline void clear_page(void *addr)
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{
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unsigned int i;
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for (i = 0; i < PAGE_SIZE / L1_CACHE_BYTES; i++, addr += L1_CACHE_BYTES)
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dcbz(addr);
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}
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extern void copy_page(void *to, void *from);
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#include <asm-generic/getorder.h>
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#define PGD_T_LOG2 (__builtin_ffs(sizeof(pgd_t)) - 1)
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#define PTE_T_LOG2 (__builtin_ffs(sizeof(pte_t)) - 1)
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_POWERPC_PAGE_32_H */
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