246 lines
4 KiB
ArmAsm
246 lines
4 KiB
ArmAsm
/*
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* Floating-point, VMX/Altivec and VSX loads and stores
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* for use in instruction emulation.
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*
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* Copyright 2010 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/processor.h>
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#include <asm/ppc_asm.h>
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#include <asm/ppc-opcode.h>
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#include <asm/reg.h>
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#include <asm/asm-offsets.h>
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#include <asm/asm-compat.h>
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#include <linux/errno.h>
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#ifdef CONFIG_PPC_FPU
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#define STKFRM (PPC_MIN_STKFRM + 16)
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/* Get the contents of frN into *p; N is in r3 and p is in r4. */
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_GLOBAL(get_fpr)
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mflr r0
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mfmsr r6
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ori r7, r6, MSR_FP
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MTMSRD(r7)
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isync
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rlwinm r3,r3,3,0xf8
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bcl 20,31,1f
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reg = 0
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.rept 32
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stfd reg, 0(r4)
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b 2f
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reg = reg + 1
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.endr
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1: mflr r5
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add r5,r3,r5
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mtctr r5
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mtlr r0
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bctr
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2: MTMSRD(r6)
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isync
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blr
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/* Put the contents of *p into frN; N is in r3 and p is in r4. */
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_GLOBAL(put_fpr)
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mflr r0
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mfmsr r6
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ori r7, r6, MSR_FP
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MTMSRD(r7)
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isync
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rlwinm r3,r3,3,0xf8
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bcl 20,31,1f
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reg = 0
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.rept 32
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lfd reg, 0(r4)
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b 2f
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reg = reg + 1
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.endr
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1: mflr r5
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add r5,r3,r5
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mtctr r5
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mtlr r0
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bctr
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2: MTMSRD(r6)
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isync
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blr
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#ifdef CONFIG_ALTIVEC
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/* Get the contents of vrN into *p; N is in r3 and p is in r4. */
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_GLOBAL(get_vr)
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mflr r0
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mfmsr r6
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oris r7, r6, MSR_VEC@h
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MTMSRD(r7)
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isync
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rlwinm r3,r3,3,0xf8
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bcl 20,31,1f
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reg = 0
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.rept 32
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stvx reg, 0, r4
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b 2f
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reg = reg + 1
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.endr
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1: mflr r5
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add r5,r3,r5
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mtctr r5
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mtlr r0
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bctr
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2: MTMSRD(r6)
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isync
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blr
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/* Put the contents of *p into vrN; N is in r3 and p is in r4. */
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_GLOBAL(put_vr)
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mflr r0
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mfmsr r6
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oris r7, r6, MSR_VEC@h
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MTMSRD(r7)
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isync
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rlwinm r3,r3,3,0xf8
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bcl 20,31,1f
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reg = 0
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.rept 32
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lvx reg, 0, r4
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b 2f
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reg = reg + 1
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.endr
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1: mflr r5
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add r5,r3,r5
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mtctr r5
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mtlr r0
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bctr
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2: MTMSRD(r6)
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isync
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blr
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#endif /* CONFIG_ALTIVEC */
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#ifdef CONFIG_VSX
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/* Get the contents of vsN into vs0; N is in r3. */
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_GLOBAL(get_vsr)
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mflr r0
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rlwinm r3,r3,3,0x1f8
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bcl 20,31,1f
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blr /* vs0 is already in vs0 */
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nop
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reg = 1
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.rept 63
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XXLOR(0,reg,reg)
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blr
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reg = reg + 1
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.endr
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1: mflr r5
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add r5,r3,r5
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mtctr r5
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mtlr r0
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bctr
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/* Put the contents of vs0 into vsN; N is in r3. */
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_GLOBAL(put_vsr)
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mflr r0
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rlwinm r3,r3,3,0x1f8
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bcl 20,31,1f
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blr /* v0 is already in v0 */
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nop
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reg = 1
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.rept 63
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XXLOR(reg,0,0)
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blr
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reg = reg + 1
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.endr
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1: mflr r5
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add r5,r3,r5
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mtctr r5
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mtlr r0
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bctr
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/* Load VSX reg N from vector doubleword *p. N is in r3, p in r4. */
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_GLOBAL(load_vsrn)
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PPC_STLU r1,-STKFRM(r1)
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mflr r0
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PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
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mfmsr r6
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oris r7,r6,MSR_VSX@h
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cmpwi cr7,r3,0
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li r8,STKFRM-16
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MTMSRD(r7)
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isync
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beq cr7,1f
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STXVD2X(0,R1,R8)
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1: LXVD2X(0,R0,R4)
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#ifdef __LITTLE_ENDIAN__
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XXSWAPD(0,0)
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#endif
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beq cr7,4f
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bl put_vsr
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LXVD2X(0,R1,R8)
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4: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1)
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mtlr r0
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MTMSRD(r6)
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isync
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addi r1,r1,STKFRM
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blr
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/* Store VSX reg N to vector doubleword *p. N is in r3, p in r4. */
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_GLOBAL(store_vsrn)
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PPC_STLU r1,-STKFRM(r1)
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mflr r0
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PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
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mfmsr r6
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oris r7,r6,MSR_VSX@h
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li r8,STKFRM-16
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MTMSRD(r7)
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isync
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STXVD2X(0,R1,R8)
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bl get_vsr
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#ifdef __LITTLE_ENDIAN__
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XXSWAPD(0,0)
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#endif
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STXVD2X(0,R0,R4)
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LXVD2X(0,R1,R8)
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PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1)
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mtlr r0
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MTMSRD(r6)
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isync
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mr r3,r9
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addi r1,r1,STKFRM
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blr
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#endif /* CONFIG_VSX */
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/* Convert single-precision to double, without disturbing FPRs. */
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/* conv_sp_to_dp(float *sp, double *dp) */
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_GLOBAL(conv_sp_to_dp)
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mfmsr r6
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ori r7, r6, MSR_FP
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MTMSRD(r7)
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isync
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stfd fr0, -16(r1)
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lfs fr0, 0(r3)
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stfd fr0, 0(r4)
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lfd fr0, -16(r1)
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MTMSRD(r6)
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isync
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blr
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/* Convert single-precision to double, without disturbing FPRs. */
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/* conv_sp_to_dp(double *dp, float *sp) */
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_GLOBAL(conv_dp_to_sp)
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mfmsr r6
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ori r7, r6, MSR_FP
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MTMSRD(r7)
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isync
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stfd fr0, -16(r1)
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lfd fr0, 0(r3)
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stfs fr0, 0(r4)
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lfd fr0, -16(r1)
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MTMSRD(r6)
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isync
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blr
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#endif /* CONFIG_PPC_FPU */
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