193 lines
5.4 KiB
C
193 lines
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* pci_impl.h: Helper definitions for PCI controller support.
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*
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* Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net)
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*/
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#ifndef PCI_IMPL_H
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#define PCI_IMPL_H
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include <linux/pci.h>
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#include <linux/msi.h>
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#include <linux/of_device.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/iommu.h>
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/* The abstraction used here is that there are PCI controllers,
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* each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
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* underneath. Each PCI bus module uses an IOMMU (shared by both
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* PBMs of a controller, or per-PBM), and if a streaming buffer
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* is present, each PCI bus module has it's own. (ie. the IOMMU
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* might be shared between PBMs, the STC is never shared)
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* Furthermore, each PCI bus module controls it's own autonomous
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* PCI bus.
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*/
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#define PCI_STC_FLUSHFLAG_INIT(STC) \
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(*((STC)->strbuf_flushflag) = 0UL)
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#define PCI_STC_FLUSHFLAG_SET(STC) \
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(*((STC)->strbuf_flushflag) != 0UL)
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#ifdef CONFIG_PCI_MSI
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struct pci_pbm_info;
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struct sparc64_msiq_ops {
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int (*get_head)(struct pci_pbm_info *pbm, unsigned long msiqid,
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unsigned long *head);
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int (*dequeue_msi)(struct pci_pbm_info *pbm, unsigned long msiqid,
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unsigned long *head, unsigned long *msi);
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int (*set_head)(struct pci_pbm_info *pbm, unsigned long msiqid,
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unsigned long head);
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int (*msi_setup)(struct pci_pbm_info *pbm, unsigned long msiqid,
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unsigned long msi, int is_msi64);
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int (*msi_teardown)(struct pci_pbm_info *pbm, unsigned long msi);
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int (*msiq_alloc)(struct pci_pbm_info *pbm);
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void (*msiq_free)(struct pci_pbm_info *pbm);
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int (*msiq_build_irq)(struct pci_pbm_info *pbm, unsigned long msiqid,
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unsigned long devino);
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};
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void sparc64_pbm_msi_init(struct pci_pbm_info *pbm,
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const struct sparc64_msiq_ops *ops);
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struct sparc64_msiq_cookie {
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struct pci_pbm_info *pbm;
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unsigned long msiqid;
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};
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#endif
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struct pci_pbm_info {
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struct pci_pbm_info *next;
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struct pci_pbm_info *sibling;
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int index;
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/* Physical address base of controller registers. */
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unsigned long controller_regs;
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/* Physical address base of PBM registers. */
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unsigned long pbm_regs;
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/* Physical address of DMA sync register, if any. */
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unsigned long sync_reg;
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/* Opaque 32-bit system bus Port ID. */
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u32 portid;
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/* Opaque 32-bit handle used for hypervisor calls. */
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u32 devhandle;
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/* Chipset version information. */
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int chip_type;
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#define PBM_CHIP_TYPE_SABRE 1
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#define PBM_CHIP_TYPE_PSYCHO 2
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#define PBM_CHIP_TYPE_SCHIZO 3
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#define PBM_CHIP_TYPE_SCHIZO_PLUS 4
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#define PBM_CHIP_TYPE_TOMATILLO 5
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int chip_version;
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int chip_revision;
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/* Name used for top-level resources. */
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const char *name;
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/* OBP specific information. */
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struct platform_device *op;
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u64 ino_bitmap;
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/* PBM I/O and Memory space resources. */
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struct resource io_space;
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struct resource mem_space;
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struct resource mem64_space;
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struct resource busn;
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/* offset */
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resource_size_t io_offset;
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resource_size_t mem_offset;
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resource_size_t mem64_offset;
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/* Base of PCI Config space, can be per-PBM or shared. */
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unsigned long config_space;
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/* This will be 12 on PCI-E controllers, 8 elsewhere. */
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unsigned long config_space_reg_bits;
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unsigned long pci_afsr;
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unsigned long pci_afar;
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unsigned long pci_csr;
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/* State of 66MHz capabilities on this PBM. */
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int is_66mhz_capable;
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int all_devs_66mhz;
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#ifdef CONFIG_PCI_MSI
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/* MSI info. */
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u32 msiq_num;
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u32 msiq_ent_count;
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u32 msiq_first;
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u32 msiq_first_devino;
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u32 msiq_rotor;
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struct sparc64_msiq_cookie *msiq_irq_cookies;
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u32 msi_num;
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u32 msi_first;
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u32 msi_data_mask;
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u32 msix_data_width;
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u64 msi32_start;
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u64 msi64_start;
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u32 msi32_len;
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u32 msi64_len;
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void *msi_queues;
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unsigned long *msi_bitmap;
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unsigned int *msi_irq_table;
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int (*setup_msi_irq)(unsigned int *irq_p, struct pci_dev *pdev,
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struct msi_desc *entry);
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void (*teardown_msi_irq)(unsigned int irq, struct pci_dev *pdev);
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const struct sparc64_msiq_ops *msi_ops;
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#endif /* !(CONFIG_PCI_MSI) */
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/* This PBM's streaming buffer. */
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struct strbuf stc;
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/* IOMMU state, potentially shared by both PBM segments. */
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struct iommu *iommu;
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/* Now things for the actual PCI bus probes. */
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unsigned int pci_first_busno;
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unsigned int pci_last_busno;
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struct pci_bus *pci_bus;
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struct pci_ops *pci_ops;
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int numa_node;
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};
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extern struct pci_pbm_info *pci_pbm_root;
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extern int pci_num_pbms;
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/* PCI bus scanning and fixup support. */
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void pci_get_pbm_props(struct pci_pbm_info *pbm);
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struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
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struct device *parent);
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void pci_determine_mem_io_space(struct pci_pbm_info *pbm);
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/* Error reporting support. */
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void pci_scan_for_target_abort(struct pci_pbm_info *, struct pci_bus *);
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void pci_scan_for_master_abort(struct pci_pbm_info *, struct pci_bus *);
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void pci_scan_for_parity_error(struct pci_pbm_info *, struct pci_bus *);
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/* Configuration space access. */
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void pci_config_read8(u8 *addr, u8 *ret);
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void pci_config_read16(u16 *addr, u16 *ret);
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void pci_config_read32(u32 *addr, u32 *ret);
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void pci_config_write8(u8 *addr, u8 val);
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void pci_config_write16(u16 *addr, u16 val);
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void pci_config_write32(u32 *addr, u32 val);
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extern struct pci_ops sun4u_pci_ops;
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extern struct pci_ops sun4v_pci_ops;
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extern volatile int pci_poke_in_progress;
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extern volatile int pci_poke_cpu;
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extern volatile int pci_poke_faulted;
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#endif /* !(PCI_IMPL_H) */
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