210 lines
4.9 KiB
C
210 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/soc/mediatek/mtk_dvfsrc.h>
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#include "dvfsrc-met.h"
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#include "dvfsrc-common.h"
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static inline u32 dvfsrc_met_read(struct mtk_dvfsrc_met *dvfs, u32 offset)
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{
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return readl(dvfs->regs + offset);
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}
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enum met_src_index {
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SRC_MD2SPM_IDX,
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DDR_SW_REQ1_PMQOS_IDX,
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DDR_SW_REQ2_CM_IDX,
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DDR_EMI_TOTAL_IDX,
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DDR_QOS_BW_IDX,
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VCORE_SW_REQ1_PMQOS_IDX,
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VCORE_SW_REQ2_CM_IDX,
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VCORE_SCP_IDX,
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SRC_PMQOS_TOTAL_IDX,
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SRC_PMQOS_BW0_IDX,
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SRC_PMQOS_BW1_IDX,
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SRC_PMQOS_BW2_IDX,
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SRC_PMQOS_BW3_IDX,
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SRC_PMQOS_BW4_IDX,
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SRC_MD_REQ_OPP,
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SRC_MAX
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};
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/* met profile table */
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static unsigned int met_vcorefs_src[SRC_MAX];
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char *met_src_name[SRC_MAX] = {
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"MD2SPM",
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"DDR__SW_REQ1_PMQOS",
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"DDR__SW_REQ2_CM",
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"DDR__EMI_TOTAL",
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"DDR__QOS_BW",
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"VCORE__SW_REQ1_PMQOS",
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"VCORE__SW_REQ2_CM",
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"VCORE__SCP",
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"PMQOS_TOTAL",
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"PMQOS_BW0",
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"PMQOS_BW1",
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"PMQOS_BW2",
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"PMQOS_BW3",
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"PMQOS_BW4",
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"MD_REQ_OPP",
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};
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#define DVFSRC_SW_REQ1 (0x4)
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#define DVFSRC_SW_REQ2 (0x8)
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#define DVFSRC_VCORE_REQUEST (0x48)
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#define DVFSRC_EMI_QOS0 (0x24)
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#define DVFSRC_EMI_QOS1 (0x28)
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#define DVFSRC_SW_BW_0 (0x160)
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#define DVFSRC_SW_BW_1 (0x164)
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#define DVFSRC_SW_BW_2 (0x168)
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#define DVFSRC_SW_BW_3 (0x16C)
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#define DVFSRC_SW_BW_4 (0x170)
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#define DVFSRC_MD_SCENARIO (0x310)
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#define DVFSRC_RSRV_0 (0x600)
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#define DVFSRC_LEVEL (0xDC)
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#define DVFSRC_CURRENT_LEVEL(x) (((x) >> 16) & 0x0000ffff)
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/* DVFSRC_SW_REQX */
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#define EMI_SW_AP_SHIFT 0
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#define EMI_SW_AP_MASK 0x3
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#define VCORE_SW_AP_SHIFT 2
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#define VCORE_SW_AP_MASK 0x3
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/* DVFSRC_VCORE_REQUEST */
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#define VCORE_SCP_GEAR_SHIFT 30
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#define VCORE_SCP_GEAR_MASK 0x3
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/* met profile function */
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static int dvfsrc_get_src_req_num(void)
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{
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return SRC_MAX;
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}
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static char **dvfsrc_get_src_req_name(void)
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{
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return met_src_name;
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}
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static u32 dvfsrc_get_current_level(struct mtk_dvfsrc_met *dvfsrc)
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{
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return DVFSRC_CURRENT_LEVEL(dvfsrc_met_read(dvfsrc, DVFSRC_LEVEL));
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}
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static u32 dvfsrc_mt6761_ddr_qos(struct mtk_dvfsrc_met *dvfs, u32 bw)
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{
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unsigned int qos0_thres = dvfsrc_met_read(dvfs, DVFSRC_EMI_QOS0);
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unsigned int qos1_thres = dvfsrc_met_read(dvfs, DVFSRC_EMI_QOS1);
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if (bw < qos0_thres)
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return 0;
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else if (bw < qos1_thres)
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return 1;
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else
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return 2;
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}
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static int dvfsrc_mt6761_emi_mon_gear(struct mtk_dvfsrc_met *dvfs)
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{
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return 0;
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}
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static void vcorefs_get_src_ddr_req(struct mtk_dvfsrc_met *dvfs)
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{
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unsigned int sw_req;
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sw_req = dvfsrc_met_read(dvfs, DVFSRC_SW_REQ1);
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met_vcorefs_src[DDR_SW_REQ1_PMQOS_IDX] =
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(sw_req >> EMI_SW_AP_SHIFT) & EMI_SW_AP_MASK;
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sw_req = dvfsrc_met_read(dvfs, DVFSRC_SW_REQ2);
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met_vcorefs_src[DDR_SW_REQ2_CM_IDX] =
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(sw_req >> EMI_SW_AP_SHIFT) & EMI_SW_AP_MASK;
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met_vcorefs_src[DDR_EMI_TOTAL_IDX] =
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dvfsrc_mt6761_emi_mon_gear(dvfs);
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}
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static void vcorefs_get_src_vcore_req(struct mtk_dvfsrc_met *dvfs)
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{
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u32 sw_req;
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sw_req = dvfsrc_met_read(dvfs, DVFSRC_SW_REQ1);
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met_vcorefs_src[VCORE_SW_REQ1_PMQOS_IDX] =
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(sw_req >> VCORE_SW_AP_SHIFT) & VCORE_SW_AP_MASK;
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sw_req = dvfsrc_met_read(dvfs, DVFSRC_SW_REQ2);
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met_vcorefs_src[VCORE_SW_REQ2_CM_IDX] =
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(sw_req >> VCORE_SW_AP_SHIFT) & VCORE_SW_AP_MASK;
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sw_req = dvfsrc_met_read(dvfs, DVFSRC_VCORE_REQUEST);
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met_vcorefs_src[VCORE_SCP_IDX] =
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(sw_req >> VCORE_SCP_GEAR_SHIFT) & VCORE_SCP_GEAR_MASK;
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}
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static void vcorefs_get_src_misc_info(struct mtk_dvfsrc_met *dvfs)
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{
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u32 qos_bw0, qos_bw1, qos_bw2, qos_bw3, qos_bw4;
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u32 total_bw;
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qos_bw0 = dvfsrc_met_read(dvfs, DVFSRC_SW_BW_0);
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qos_bw1 = dvfsrc_met_read(dvfs, DVFSRC_SW_BW_1);
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qos_bw2 = dvfsrc_met_read(dvfs, DVFSRC_SW_BW_2);
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qos_bw3 = dvfsrc_met_read(dvfs, DVFSRC_SW_BW_3);
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qos_bw4 = dvfsrc_met_read(dvfs, DVFSRC_SW_BW_4);
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total_bw = qos_bw0 + qos_bw1 + qos_bw2 + qos_bw3 + qos_bw4;
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met_vcorefs_src[SRC_MD2SPM_IDX] =
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dvfsrc_met_read(dvfs, DVFSRC_MD_SCENARIO);
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met_vcorefs_src[SRC_PMQOS_TOTAL_IDX] = total_bw;
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met_vcorefs_src[DDR_QOS_BW_IDX] =
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dvfsrc_mt6761_ddr_qos(dvfs, total_bw);
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met_vcorefs_src[SRC_PMQOS_BW0_IDX] = qos_bw0;
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met_vcorefs_src[SRC_PMQOS_BW1_IDX] = qos_bw1;
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met_vcorefs_src[SRC_PMQOS_BW2_IDX] = qos_bw2;
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met_vcorefs_src[SRC_PMQOS_BW3_IDX] = qos_bw3;
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met_vcorefs_src[SRC_PMQOS_BW4_IDX] = qos_bw4;
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met_vcorefs_src[SRC_MD_REQ_OPP] =
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dvfsrc_met_read(dvfs, DVFSRC_RSRV_0) & 0x3F;
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}
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static unsigned int *dvfsrc_get_src_req(struct mtk_dvfsrc_met *dvfs)
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{
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vcorefs_get_src_ddr_req(dvfs);
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vcorefs_get_src_vcore_req(dvfs);
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vcorefs_get_src_misc_info(dvfs);
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return met_vcorefs_src;
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}
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static int dvfsrc_get_ddr_ratio(struct mtk_dvfsrc_met *dvfs)
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{
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return 0;
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}
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const struct dvfsrc_met_config mt6761_met_config = {
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.dvfsrc_get_src_req_num = dvfsrc_get_src_req_num,
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.dvfsrc_get_src_req_name = dvfsrc_get_src_req_name,
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.dvfsrc_get_src_req = dvfsrc_get_src_req,
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.dvfsrc_get_ddr_ratio = dvfsrc_get_ddr_ratio,
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.get_current_level = dvfsrc_get_current_level,
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};
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