324 lines
7.4 KiB
C
324 lines
7.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/soc/mediatek/mtk_dvfsrc.h>
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#include "dvfsrc-met.h"
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#include "dvfsrc-common.h"
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static inline u32 dvfsrc_met_read(struct mtk_dvfsrc_met *dvfs, u32 offset)
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{
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return readl(dvfs->regs + offset);
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}
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enum met_src_index {
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SRC_MD2SPM_IDX = 0,
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DDR_SW_REQ1_SPM_IDX,
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DDR_SW_REQ2_CM_IDX,
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DDR_SW_REQ3_PMQOS_IDX,
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DDR_SW_REQ4_MD_IDX,
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DDR_SW_REQ8_MCUSYS_IDX,
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DDR_QOS_BW_IDX,
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DDR_EMI_TOTAL_IDX,
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DDR_HRT_BW_IDX,
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DDR_HIFI_IDX,
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DDR_HIFI_LATENCY_IDX,
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DDR_MD_LATENCY_IDX,
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VCORE_SW_REQ3_PMQOS_IDX,
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VCORE_SCP_IDX,
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VCORE_HIFI_IDX,
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SRC_SCP_REQ_IDX,
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SRC_PMQOS_TATOL_IDX,
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SRC_PMQOS_BW0_IDX,
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SRC_PMQOS_BW1_IDX,
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SRC_PMQOS_BW2_IDX,
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SRC_PMQOS_BW3_IDX,
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SRC_PMQOS_BW4_IDX,
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SRC_HRT_MD_BW_IDX,
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SRC_HRT_DISP_BW_IDX,
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SRC_HRT_ISP_BW_IDX,
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SRC_MD_SCENARIO_IDX,
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SRC_HIFI_SCENARIO_IDX,
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SRC_MD_EMI_LATENCY_IDX,
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SRC_MAX
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};
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/* met profile table */
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static unsigned int met_vcorefs_src[SRC_MAX];
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static char *met_src_name[SRC_MAX] = {
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"MD2SPM",
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"DDR__SW_REQ1_SPM",
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"DDR__SW_REQ2_CM",
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"DDR__SW_REQ3_PMQOS",
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"DDR__SW_REQ4_MD",
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"DDR__SW_REQ8_MCUSYS",
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"DDR__QOS_BW",
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"DDR__EMI_TOTAL",
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"DDR__HRT_BW",
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"DDR__HIFI",
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"DDR__HIFI_LATENCY",
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"DDR__MD_LATENCY",
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"VCORE__SW_REQ3_PMQOS",
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"VCORE__SCP",
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"VCORE__HIFI",
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"SCP_REQ",
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"PMQOS_TATOL",
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"PMQOS_BW0",
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"PMQOS_BW1",
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"PMQOS_BW2",
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"PMQOS_BW3",
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"PMQOS_BW4",
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"HRT_MD_BW",
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"HRT_DISP_BW",
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"HRT_ISP_BW",
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"MD_SCENARIO",
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"HIFI_SCENARIO_IDX",
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"MD_EMI_LATENCY",
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};
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#define DVFSRC_SW_REQ1 (0x4)
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#define DVFSRC_SW_REQ2 (0x8)
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#define DVFSRC_SW_REQ3 (0xC)
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#define DVFSRC_SW_REQ4 (0x10)
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#define DVFSRC_SW_REQ5 (0x14)
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#define DVFSRC_SW_REQ6 (0x18)
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#define DVFSRC_SW_REQ7 (0x1C)
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#define DVFSRC_SW_REQ8 (0x20)
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#define DVFSRC_ISP_HRT (0x290)
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#define DVFSRC_VCORE_REQUEST (0x6C)
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#define DVFSRC_DEBUG_STA_0 (0x700)
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#define DVFSRC_DEBUG_STA_2 (0x708)
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#define DVFSRC_SW_BW_0 (0x260)
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#define DVFSRC_SW_BW_1 (0x264)
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#define DVFSRC_SW_BW_2 (0x268)
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#define DVFSRC_SW_BW_3 (0x26C)
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#define DVFSRC_SW_BW_4 (0x270)
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#define DVFSRC_CURRENT_LEVEL (0xD44)
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/* DVFSRC_SW_REQX */
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#define DDR_SW_AP_SHIFT 12
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#define DDR_SW_AP_MASK 0x7
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#define VCORE_SW_AP_SHIFT 4
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#define VCORE_SW_AP_MASK 0x7
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/* DVFSRC_VCORE_REQUEST 0x70 */
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#define VCORE_SCP_GEAR_SHIFT 12
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#define VCORE_SCP_GEAR_MASK 0x7
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/* met profile function */
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static int dvfsrc_get_src_req_num(void)
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{
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return SRC_MAX;
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}
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static char **dvfsrc_get_src_req_name(void)
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{
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return met_src_name;
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}
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static u32 dvfsrc_get_current_level(struct mtk_dvfsrc_met *dvfsrc)
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{
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return dvfsrc_met_read(dvfsrc, DVFSRC_CURRENT_LEVEL);
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}
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static u32 dvfsrc_mt6779_ddr_qos(struct mtk_dvfsrc_met *dvfs)
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{
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unsigned int qos_total_bw = dvfsrc_met_read(dvfs, DVFSRC_SW_BW_0) +
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dvfsrc_met_read(dvfs, DVFSRC_SW_BW_1) +
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dvfsrc_met_read(dvfs, DVFSRC_SW_BW_2) +
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dvfsrc_met_read(dvfs, DVFSRC_SW_BW_3) +
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dvfsrc_met_read(dvfs, DVFSRC_SW_BW_4);
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if (qos_total_bw < 0x19)
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return 0;
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else if (qos_total_bw < 0x26)
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return 2;
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else if (qos_total_bw < 0x33)
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return 2;
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else if (qos_total_bw < 0x4c)
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return 3;
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else if (qos_total_bw < 0x66)
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return 4;
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else
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return 5;
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}
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static int dvfsrc_mt6779_emi_mon_gear(struct mtk_dvfsrc_met *dvfs)
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{
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unsigned int total_bw_status;
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int i;
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total_bw_status = dvfsrc_met_read(dvfs, DVFSRC_DEBUG_STA_2) & 0x1F;
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for (i = 4; i >= 0 ; i--) {
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if ((total_bw_status >> i) > 0) {
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if (i == 0)
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return i + 2;
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else
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return i + 1;
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}
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}
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return 0;
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}
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static void vcorefs_get_src_ddr_req(struct mtk_dvfsrc_met *dvfs)
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{
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unsigned int sw_req;
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sw_req = dvfsrc_met_read(dvfs, DVFSRC_SW_REQ1);
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met_vcorefs_src[DDR_SW_REQ1_SPM_IDX] =
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(sw_req >> DDR_SW_AP_SHIFT) & DDR_SW_AP_MASK;
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sw_req = dvfsrc_met_read(dvfs, DVFSRC_SW_REQ2);
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met_vcorefs_src[DDR_SW_REQ2_CM_IDX] =
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(sw_req >> DDR_SW_AP_SHIFT) & DDR_SW_AP_MASK;
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sw_req = dvfsrc_met_read(dvfs, DVFSRC_SW_REQ3);
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met_vcorefs_src[DDR_SW_REQ3_PMQOS_IDX] =
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(sw_req >> DDR_SW_AP_SHIFT) & DDR_SW_AP_MASK;
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sw_req = dvfsrc_met_read(dvfs, DVFSRC_SW_REQ4);
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met_vcorefs_src[DDR_SW_REQ4_MD_IDX] =
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(sw_req >> DDR_SW_AP_SHIFT) & DDR_SW_AP_MASK;
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sw_req = dvfsrc_met_read(dvfs, DVFSRC_SW_REQ8);
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met_vcorefs_src[DDR_SW_REQ8_MCUSYS_IDX] =
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(sw_req >> DDR_SW_AP_SHIFT) & DDR_SW_AP_MASK;
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met_vcorefs_src[DDR_QOS_BW_IDX] =
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dvfsrc_mt6779_ddr_qos(dvfs);
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met_vcorefs_src[DDR_EMI_TOTAL_IDX] =
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dvfsrc_mt6779_emi_mon_gear(dvfs);
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met_vcorefs_src[DDR_HRT_BW_IDX] =
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mtk_dvfsrc_query_debug_info(DVFSRC_HRT_BW_DDR_REQ);
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met_vcorefs_src[DDR_HIFI_IDX] =
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mtk_dvfsrc_query_debug_info(DVFSRC_HIFI_DDR_REQ);
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met_vcorefs_src[DDR_HIFI_LATENCY_IDX] =
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mtk_dvfsrc_query_debug_info(DVFSRC_HIFI_RISING_DDR_REQ);
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met_vcorefs_src[DDR_MD_LATENCY_IDX] =
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mtk_dvfsrc_query_debug_info(DVFSRC_MD_RISING_DDR_REQ);
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}
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static void vcorefs_get_src_vcore_req(struct mtk_dvfsrc_met *dvfs)
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{
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u32 sw_req;
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u32 scp_en;
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scp_en = (dvfsrc_met_read(dvfs, DVFSRC_DEBUG_STA_2) >> 14) & 0x1;
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sw_req = dvfsrc_met_read(dvfs, DVFSRC_SW_REQ3);
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met_vcorefs_src[VCORE_SW_REQ3_PMQOS_IDX] =
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(sw_req >> VCORE_SW_AP_SHIFT) & VCORE_SW_AP_MASK;
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if (scp_en) {
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sw_req = dvfsrc_met_read(dvfs, DVFSRC_VCORE_REQUEST);
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met_vcorefs_src[VCORE_SCP_IDX] =
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(sw_req >> VCORE_SCP_GEAR_SHIFT) & VCORE_SCP_GEAR_MASK;
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} else
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met_vcorefs_src[VCORE_SCP_IDX] = 0;
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met_vcorefs_src[VCORE_HIFI_IDX] =
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mtk_dvfsrc_query_debug_info(DVFSRC_HIFI_VCORE_REQ);
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}
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static void vcorefs_get_src_misc_info(struct mtk_dvfsrc_met *dvfs)
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{
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u32 qos_bw0, qos_bw1, qos_bw2, qos_bw3, qos_bw4;
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u32 sta0, sta2;
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qos_bw0 = dvfsrc_met_read(dvfs, DVFSRC_SW_BW_0);
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qos_bw1 = dvfsrc_met_read(dvfs, DVFSRC_SW_BW_1);
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qos_bw2 = dvfsrc_met_read(dvfs, DVFSRC_SW_BW_2);
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qos_bw3 = dvfsrc_met_read(dvfs, DVFSRC_SW_BW_3);
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qos_bw4 = dvfsrc_met_read(dvfs, DVFSRC_SW_BW_4);
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sta0 = dvfsrc_met_read(dvfs, DVFSRC_DEBUG_STA_0);
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sta2 = dvfsrc_met_read(dvfs, DVFSRC_DEBUG_STA_2);
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met_vcorefs_src[SRC_MD2SPM_IDX] =
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sta0 & 0xFFFF;
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met_vcorefs_src[SRC_SCP_REQ_IDX] =
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(sta2 >> 14) & 0x1;
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met_vcorefs_src[SRC_PMQOS_TATOL_IDX] =
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qos_bw0 + qos_bw1 + qos_bw2 + qos_bw3 + qos_bw4;
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met_vcorefs_src[SRC_PMQOS_BW0_IDX] =
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qos_bw0;
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met_vcorefs_src[SRC_PMQOS_BW1_IDX] =
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qos_bw1;
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met_vcorefs_src[SRC_PMQOS_BW2_IDX] =
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qos_bw2;
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met_vcorefs_src[SRC_PMQOS_BW3_IDX] =
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qos_bw3;
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met_vcorefs_src[SRC_PMQOS_BW4_IDX] =
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qos_bw4;
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met_vcorefs_src[SRC_HRT_ISP_BW_IDX] =
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dvfsrc_met_read(dvfs, DVFSRC_ISP_HRT);
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met_vcorefs_src[SRC_MD_SCENARIO_IDX] =
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sta0 & 0xFFFF;
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met_vcorefs_src[SRC_MD_EMI_LATENCY_IDX] =
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(sta2 >> 12) & 0x3;
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met_vcorefs_src[SRC_HRT_MD_BW_IDX] =
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mtk_dvfsrc_query_debug_info(DVFSRC_MD_HRT_BW);
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met_vcorefs_src[SRC_HIFI_SCENARIO_IDX] =
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(sta2 >> 16) & 0xFF;
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}
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static unsigned int *dvfsrc_get_src_req(struct mtk_dvfsrc_met *dvfs)
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{
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vcorefs_get_src_ddr_req(dvfs);
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vcorefs_get_src_vcore_req(dvfs);
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vcorefs_get_src_misc_info(dvfs);
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return met_vcorefs_src;
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}
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static int dvfsrc_get_ddr_ratio(struct mtk_dvfsrc_met *dvfs)
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{
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int level, dram_opp;
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level = mtk_dvfsrc_query_opp_info(MTK_DVFSRC_CURR_DVFS_OPP);
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dram_opp = mtk_dvfsrc_query_opp_info(MTK_DVFSRC_CURR_DRAM_OPP);
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if ((dram_opp < 3) || (level == 10))
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return 8;
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else
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return 4;
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}
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const struct dvfsrc_met_config mt6779_met_config = {
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.dvfsrc_get_src_req_num = dvfsrc_get_src_req_num,
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.dvfsrc_get_src_req_name = dvfsrc_get_src_req_name,
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.dvfsrc_get_src_req = dvfsrc_get_src_req,
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.dvfsrc_get_ddr_ratio = dvfsrc_get_ddr_ratio,
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.get_current_level = dvfsrc_get_current_level,
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};
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