295 lines
7.6 KiB
C
295 lines
7.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#ifndef _MT753X_REGS_H_
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#define _MT753X_REGS_H_
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#include <linux/bitops.h>
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/* Values of Egress TAG Control */
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#define ETAG_CTRL_UNTAG 0
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#define ETAG_CTRL_TAG 2
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#define ETAG_CTRL_SWAP 1
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#define ETAG_CTRL_STACK 3
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#define VTCR 0x90
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#define VAWD1 0x94
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#define VAWD2 0x98
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/* Fields of VTCR */
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#define VTCR_BUSY BIT(31)
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#define IDX_INVLD BIT(16)
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#define VTCR_FUNC_S 12
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#define VTCR_FUNC_M 0xf000
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#define VTCR_VID_S 0
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#define VTCR_VID_M 0xfff
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/* Values of VTCR_FUNC */
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#define VTCR_READ_VLAN_ENTRY 0
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#define VTCR_WRITE_VLAN_ENTRY 1
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#define VTCR_INVD_VLAN_ENTRY 2
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#define VTCR_ENABLE_VLAN_ENTRY 3
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#define VTCR_READ_ACL_ENTRY 4
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#define VTCR_WRITE_ACL_ENTRY 5
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#define VTCR_READ_TRTCM_TABLE 6
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#define VTCR_WRITE_TRTCM_TABLE 7
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#define VTCR_READ_ACL_MASK_ENTRY 8
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#define VTCR_WRITE_ACL_MASK_ENTRY 9
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#define VTCR_READ_ACL_RULE_ENTRY 10
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#define VTCR_WRITE_ACL_RULE_ENTRY 11
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#define VTCR_READ_ACL_RATE_ENTRY 12
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#define VTCR_WRITE_ACL_RATE_ENTRY 13
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/* VLAN entry fields */
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/* VAWD1 */
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#define PORT_STAG BIT(31)
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#define IVL_MAC BIT(30)
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#define EG_CON BIT(29)
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#define VTAG_EN BIT(28)
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#define COPY_PRI BIT(27)
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#define USER_PRI_S 24
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#define USER_PRI_M 0x7000000
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#define PORT_MEM_S 16
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#define PORT_MEM_M 0xff0000
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#define S_TAG1_S 4
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#define S_TAG1_M 0xfff0
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#define FID_S 1
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#define FID_M 0x0e
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#define VENTRY_VALID BIT(0)
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/* VAWD2 */
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#define S_TAG2_S 16
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#define S_TAG2_M 0xffff0000
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#define PORT_ETAG_S(p) ((p) * 2)
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#define PORT_ETAG_M 0x03
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#define PORT_CTRL_BASE 0x2000
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#define PORT_CTRL_PORT_OFFSET 0x100
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#define PORT_CTRL_REG(p, r) (PORT_CTRL_BASE + \
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(p) * PORT_CTRL_PORT_OFFSET + (r))
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#define CKGCR(p) PORT_CTRL_REG(p, 0x00)
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#define PCR(p) PORT_CTRL_REG(p, 0x04)
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#define PIC(p) PORT_CTRL_REG(p, 0x08)
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#define PSC(p) PORT_CTRL_REG(p, 0x0c)
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#define PVC(p) PORT_CTRL_REG(p, 0x10)
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#define PPBV1(p) PORT_CTRL_REG(p, 0x14)
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#define PPBV2(p) PORT_CTRL_REG(p, 0x18)
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#define BSR(p) PORT_CTRL_REG(p, 0x1c)
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#define STAG01 PORT_CTRL_REG(p, 0x20)
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#define STAG23 PORT_CTRL_REG(p, 0x24)
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#define STAG45 PORT_CTRL_REG(p, 0x28)
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#define STAG67 PORT_CTRL_REG(p, 0x2c)
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#define PPBV(p, g) (PPBV1(p) + ((g) / 2) * 4)
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/* Fields of PCR */
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#define MLDV2_EN BIT(30)
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#define EG_TAG_S 28
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#define EG_TAG_M 0x30000000
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#define PORT_PRI_S 24
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#define PORT_PRI_M 0x7000000
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#define PORT_MATRIX_S 16
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#define PORT_MATRIX_M 0xff0000
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#define UP2DSCP_EN BIT(12)
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#define UP2TAG_EN BIT(11)
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#define ACL_EN BIT(10)
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#define PORT_TX_MIR BIT(9)
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#define PORT_RX_MIR BIT(8)
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#define ACL_MIR BIT(7)
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#define MIS_PORT_FW_S 4
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#define MIS_PORT_FW_M 0x70
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#define VLAN_MIS BIT(2)
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#define PORT_VLAN_S 0
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#define PORT_VLAN_M 0x03
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/* Values of PORT_VLAN */
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#define PORT_MATRIX_MODE 0
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#define FALLBACK_MODE 1
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#define CHECK_MODE 2
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#define SECURITY_MODE 3
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/* Fields of PVC */
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#define STAG_VPID_S 16
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#define STAG_VPID_M 0xffff0000
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#define DIS_PVID BIT(15)
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#define FORCE_PVID BIT(14)
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#define PT_VPM BIT(12)
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#define PT_OPTION BIT(11)
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#define PVC_EG_TAG_S 8
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#define PVC_EG_TAG_M 0x700
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#define VLAN_ATTR_S 6
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#define VLAN_ATTR_M 0xc0
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#define PVC_PORT_STAG BIT(5)
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#define BC_LKYV_EN BIT(4)
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#define MC_LKYV_EN BIT(3)
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#define UC_LKYV_EN BIT(2)
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#define ACC_FRM_S 0
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#define ACC_FRM_M 0x03
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/* Values of VLAN_ATTR */
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#define VA_USER_PORT 0
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#define VA_STACK_PORT 1
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#define VA_TRANSLATION_PORT 2
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#define VA_TRANSPARENT_PORT 3
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/* Fields of PPBV */
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#define GRP_PORT_PRI_S(g) (((g) % 2) * 16 + 13)
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#define GRP_PORT_PRI_M 0x07
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#define GRP_PORT_VID_S(g) (((g) % 2) * 16)
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#define GRP_PORT_VID_M 0xfff
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#define PORT_MAC_CTRL_BASE 0x3000
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#define PORT_MAC_CTRL_PORT_OFFSET 0x100
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#define PORT_MAC_CTRL_REG(p, r) (PORT_MAC_CTRL_BASE + \
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(p) * PORT_MAC_CTRL_PORT_OFFSET + (r))
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#define PMCR(p) PORT_MAC_CTRL_REG(p, 0x00)
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#define PMEEECR(p) PORT_MAC_CTRL_REG(p, 0x04)
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#define PMSR(p) PORT_MAC_CTRL_REG(p, 0x08)
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#define PINT_EN(p) PORT_MAC_CTRL_REG(p, 0x10)
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#define PINT_STS(p) PORT_MAC_CTRL_REG(p, 0x14)
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#define GMACCR (PORT_MAC_CTRL_BASE + 0xe0)
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#define TXCRC_EN BIT(19)
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#define RXCRC_EN BIT(18)
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#define PRMBL_LMT_EN BIT(17)
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#define MTCC_LMT_S 9
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#define MTCC_LMT_M 0x1e00
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#define MAX_RX_JUMBO_S 2
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#define MAX_RX_JUMBO_M 0x3c
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#define MAX_RX_PKT_LEN_S 0
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#define MAX_RX_PKT_LEN_M 0x3
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/* Values of MAX_RX_PKT_LEN */
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#define RX_PKT_LEN_1518 0
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#define RX_PKT_LEN_1536 1
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#define RX_PKT_LEN_1522 2
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#define RX_PKT_LEN_MAX_JUMBO 3
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/* Fields of PMCR */
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#define IPG_CFG_S 18
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#define IPG_CFG_M 0xc0000
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#define EXT_PHY BIT(17)
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#define MAC_MODE BIT(16)
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#define MAC_TX_EN BIT(14)
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#define MAC_RX_EN BIT(13)
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#define MAC_PRE BIT(11)
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#define BKOFF_EN BIT(9)
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#define BACKPR_EN BIT(8)
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#define FORCE_EEE1G BIT(7)
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#define FORCE_EEE1000 BIT(6)
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#define FORCE_RX_FC BIT(5)
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#define FORCE_TX_FC BIT(4)
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#define FORCE_SPD_S 2
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#define FORCE_SPD_M 0x0c
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#define FORCE_DPX BIT(1)
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#define FORCE_LINK BIT(0)
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/* Fields of PMSR */
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#define EEE1G_STS BIT(7)
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#define EEE100_STS BIT(6)
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#define RX_FC_STS BIT(5)
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#define TX_FC_STS BIT(4)
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#define MAC_SPD_STS_S 2
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#define MAC_SPD_STS_M 0x0c
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#define MAC_DPX_STS BIT(1)
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#define MAC_LNK_STS BIT(0)
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/* Values of MAC_SPD_STS */
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#define MAC_SPD_10 0
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#define MAC_SPD_100 1
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#define MAC_SPD_1000 2
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#define MAC_SPD_2500 3
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/* Values of IPG_CFG */
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#define IPG_96BIT 0
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#define IPG_96BIT_WITH_SHORT_IPG 1
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#define IPG_64BIT 2
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#define MIB_COUNTER_BASE 0x4000
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#define MIB_COUNTER_PORT_OFFSET 0x100
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#define MIB_COUNTER_REG(p, r) (MIB_COUNTER_BASE + \
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(p) * MIB_COUNTER_PORT_OFFSET + (r))
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#define STATS_TDPC 0x00
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#define STATS_TCRC 0x04
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#define STATS_TUPC 0x08
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#define STATS_TMPC 0x0C
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#define STATS_TBPC 0x10
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#define STATS_TCEC 0x14
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#define STATS_TSCEC 0x18
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#define STATS_TMCEC 0x1C
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#define STATS_TDEC 0x20
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#define STATS_TLCEC 0x24
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#define STATS_TXCEC 0x28
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#define STATS_TPPC 0x2C
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#define STATS_TL64PC 0x30
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#define STATS_TL65PC 0x34
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#define STATS_TL128PC 0x38
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#define STATS_TL256PC 0x3C
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#define STATS_TL512PC 0x40
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#define STATS_TL1024PC 0x44
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#define STATS_TOC 0x48
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#define STATS_RDPC 0x60
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#define STATS_RFPC 0x64
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#define STATS_RUPC 0x68
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#define STATS_RMPC 0x6C
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#define STATS_RBPC 0x70
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#define STATS_RAEPC 0x74
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#define STATS_RCEPC 0x78
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#define STATS_RUSPC 0x7C
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#define STATS_RFEPC 0x80
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#define STATS_ROSPC 0x84
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#define STATS_RJEPC 0x88
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#define STATS_RPPC 0x8C
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#define STATS_RL64PC 0x90
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#define STATS_RL65PC 0x94
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#define STATS_RL128PC 0x98
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#define STATS_RL256PC 0x9C
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#define STATS_RL512PC 0xA0
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#define STATS_RL1024PC 0xA4
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#define STATS_ROC 0xA8
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#define STATS_RDPC_CTRL 0xB0
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#define STATS_RDPC_ING 0xB4
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#define STATS_RDPC_ARL 0xB8
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#define SYS_CTRL 0x7000
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#define SW_PHY_RST BIT(2)
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#define SW_SYS_RST BIT(1)
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#define SW_REG_RST BIT(0)
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#define SYS_INT_EN 0x7008
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#define SYS_INT_STS 0x700c
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#define MAC_PC_INT BIT(16)
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#define PHY_INT(p) BIT((p) + 8)
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#define PHY_LC_INT(p) BIT(p)
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#define PHY_IAC 0x701c
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#define PHY_ACS_ST BIT(31)
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#define MDIO_REG_ADDR_S 25
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#define MDIO_REG_ADDR_M 0x3e000000
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#define MDIO_PHY_ADDR_S 20
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#define MDIO_PHY_ADDR_M 0x1f00000
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#define MDIO_CMD_S 18
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#define MDIO_CMD_M 0xc0000
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#define MDIO_ST_S 16
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#define MDIO_ST_M 0x30000
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#define MDIO_RW_DATA_S 0
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#define MDIO_RW_DATA_M 0xffff
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/* MDIO_CMD: MDIO commands */
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#define MDIO_CMD_ADDR 0
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#define MDIO_CMD_WRITE 1
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#define MDIO_CMD_READ 2
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#define MDIO_CMD_READ_C45 3
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/* MDIO_ST: MDIO start field */
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#define MDIO_ST_C45 0
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#define MDIO_ST_C22 1
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#define HWSTRAP 0x7800
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#define MHWSTRAP 0x7804
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#endif /* _MT753X_REGS_H_ */
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