350 lines
11 KiB
C
350 lines
11 KiB
C
/*
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* Marvell 88SE94xx hardware specific head file
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*
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* Copyright 2007 Red Hat, Inc.
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* Copyright 2008 Marvell. <kewei@marvell.com>
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* Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
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*
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* This file is licensed under GPLv2.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the
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* License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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* USA
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*/
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#ifndef _MVS94XX_REG_H_
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#define _MVS94XX_REG_H_
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#include <linux/types.h>
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#define MAX_LINK_RATE SAS_LINK_RATE_6_0_GBPS
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enum VANIR_REVISION_ID {
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VANIR_A0_REV = 0xA0,
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VANIR_B0_REV = 0x01,
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VANIR_C0_REV = 0x02,
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VANIR_C1_REV = 0x03,
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VANIR_C2_REV = 0xC2,
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};
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enum host_registers {
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MVS_HST_CHIP_CONFIG = 0x10104, /* chip configuration */
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};
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enum hw_registers {
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MVS_GBL_CTL = 0x04, /* global control */
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MVS_GBL_INT_STAT = 0x00, /* global irq status */
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MVS_GBL_PI = 0x0C, /* ports implemented bitmask */
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MVS_PHY_CTL = 0x40, /* SOC PHY Control */
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MVS_PORTS_IMP = 0x9C, /* SOC Port Implemented */
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MVS_GBL_PORT_TYPE = 0xa0, /* port type */
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MVS_CTL = 0x100, /* SAS/SATA port configuration */
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MVS_PCS = 0x104, /* SAS/SATA port control/status */
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MVS_CMD_LIST_LO = 0x108, /* cmd list addr */
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MVS_CMD_LIST_HI = 0x10C,
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MVS_RX_FIS_LO = 0x110, /* RX FIS list addr */
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MVS_RX_FIS_HI = 0x114,
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MVS_STP_REG_SET_0 = 0x118, /* STP/SATA Register Set Enable */
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MVS_STP_REG_SET_1 = 0x11C,
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MVS_TX_CFG = 0x120, /* TX configuration */
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MVS_TX_LO = 0x124, /* TX (delivery) ring addr */
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MVS_TX_HI = 0x128,
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MVS_TX_PROD_IDX = 0x12C, /* TX producer pointer */
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MVS_TX_CONS_IDX = 0x130, /* TX consumer pointer (RO) */
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MVS_RX_CFG = 0x134, /* RX configuration */
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MVS_RX_LO = 0x138, /* RX (completion) ring addr */
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MVS_RX_HI = 0x13C,
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MVS_RX_CONS_IDX = 0x140, /* RX consumer pointer (RO) */
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MVS_INT_COAL = 0x148, /* Int coalescing config */
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MVS_INT_COAL_TMOUT = 0x14C, /* Int coalescing timeout */
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MVS_INT_STAT = 0x150, /* Central int status */
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MVS_INT_MASK = 0x154, /* Central int enable */
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MVS_INT_STAT_SRS_0 = 0x158, /* SATA register set status */
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MVS_INT_MASK_SRS_0 = 0x15C,
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MVS_INT_STAT_SRS_1 = 0x160,
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MVS_INT_MASK_SRS_1 = 0x164,
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MVS_NON_NCQ_ERR_0 = 0x168, /* SRS Non-specific NCQ Error */
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MVS_NON_NCQ_ERR_1 = 0x16C,
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MVS_CMD_ADDR = 0x170, /* Command register port (addr) */
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MVS_CMD_DATA = 0x174, /* Command register port (data) */
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MVS_MEM_PARITY_ERR = 0x178, /* Memory parity error */
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/* ports 1-3 follow after this */
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MVS_P0_INT_STAT = 0x180, /* port0 interrupt status */
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MVS_P0_INT_MASK = 0x184, /* port0 interrupt mask */
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/* ports 5-7 follow after this */
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MVS_P4_INT_STAT = 0x1A0, /* Port4 interrupt status */
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MVS_P4_INT_MASK = 0x1A4, /* Port4 interrupt enable mask */
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/* ports 1-3 follow after this */
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MVS_P0_SER_CTLSTAT = 0x1D0, /* port0 serial control/status */
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/* ports 5-7 follow after this */
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MVS_P4_SER_CTLSTAT = 0x1E0, /* port4 serial control/status */
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/* ports 1-3 follow after this */
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MVS_P0_CFG_ADDR = 0x200, /* port0 phy register address */
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MVS_P0_CFG_DATA = 0x204, /* port0 phy register data */
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/* ports 5-7 follow after this */
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MVS_P4_CFG_ADDR = 0x220, /* Port4 config address */
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MVS_P4_CFG_DATA = 0x224, /* Port4 config data */
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/* phys 1-3 follow after this */
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MVS_P0_VSR_ADDR = 0x250, /* phy0 VSR address */
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MVS_P0_VSR_DATA = 0x254, /* phy0 VSR data */
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/* phys 1-3 follow after this */
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/* multiplexing */
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MVS_P4_VSR_ADDR = 0x250, /* phy4 VSR address */
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MVS_P4_VSR_DATA = 0x254, /* phy4 VSR data */
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MVS_PA_VSR_ADDR = 0x290, /* All port VSR addr */
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MVS_PA_VSR_PORT = 0x294, /* All port VSR data */
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MVS_COMMAND_ACTIVE = 0x300,
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};
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enum pci_cfg_registers {
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PCR_PHY_CTL = 0x40,
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PCR_PHY_CTL2 = 0x90,
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PCR_DEV_CTRL = 0x78,
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PCR_LINK_STAT = 0x82,
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};
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/* SAS/SATA Vendor Specific Port Registers */
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enum sas_sata_vsp_regs {
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VSR_PHY_STAT = 0x00 * 4, /* Phy Interrupt Status */
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VSR_PHY_MODE1 = 0x01 * 4, /* phy Interrupt Enable */
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VSR_PHY_MODE2 = 0x02 * 4, /* Phy Configuration */
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VSR_PHY_MODE3 = 0x03 * 4, /* Phy Status */
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VSR_PHY_MODE4 = 0x04 * 4, /* Phy Counter 0 */
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VSR_PHY_MODE5 = 0x05 * 4, /* Phy Counter 1 */
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VSR_PHY_MODE6 = 0x06 * 4, /* Event Counter Control */
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VSR_PHY_MODE7 = 0x07 * 4, /* Event Counter Select */
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VSR_PHY_MODE8 = 0x08 * 4, /* Event Counter 0 */
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VSR_PHY_MODE9 = 0x09 * 4, /* Event Counter 1 */
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VSR_PHY_MODE10 = 0x0A * 4, /* Event Counter 2 */
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VSR_PHY_MODE11 = 0x0B * 4, /* Event Counter 3 */
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VSR_PHY_ACT_LED = 0x0C * 4, /* Activity LED control */
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VSR_PHY_FFE_CONTROL = 0x10C,
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VSR_PHY_DFE_UPDATE_CRTL = 0x110,
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VSR_REF_CLOCK_CRTL = 0x1A0,
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};
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enum chip_register_bits {
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PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0x7 << 8),
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PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0x7 << 12),
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PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (16),
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PHY_NEG_SPP_PHYS_LINK_RATE_MASK =
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(0x3 << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET),
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};
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enum pci_interrupt_cause {
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/* MAIN_IRQ_CAUSE (R10200) Bits*/
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MVS_IRQ_COM_IN_I2O_IOP0 = (1 << 0),
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MVS_IRQ_COM_IN_I2O_IOP1 = (1 << 1),
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MVS_IRQ_COM_IN_I2O_IOP2 = (1 << 2),
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MVS_IRQ_COM_IN_I2O_IOP3 = (1 << 3),
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MVS_IRQ_COM_OUT_I2O_HOS0 = (1 << 4),
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MVS_IRQ_COM_OUT_I2O_HOS1 = (1 << 5),
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MVS_IRQ_COM_OUT_I2O_HOS2 = (1 << 6),
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MVS_IRQ_COM_OUT_I2O_HOS3 = (1 << 7),
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MVS_IRQ_PCIF_TO_CPU_DRBL0 = (1 << 8),
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MVS_IRQ_PCIF_TO_CPU_DRBL1 = (1 << 9),
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MVS_IRQ_PCIF_TO_CPU_DRBL2 = (1 << 10),
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MVS_IRQ_PCIF_TO_CPU_DRBL3 = (1 << 11),
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MVS_IRQ_PCIF_DRBL0 = (1 << 12),
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MVS_IRQ_PCIF_DRBL1 = (1 << 13),
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MVS_IRQ_PCIF_DRBL2 = (1 << 14),
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MVS_IRQ_PCIF_DRBL3 = (1 << 15),
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MVS_IRQ_XOR_A = (1 << 16),
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MVS_IRQ_XOR_B = (1 << 17),
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MVS_IRQ_SAS_A = (1 << 18),
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MVS_IRQ_SAS_B = (1 << 19),
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MVS_IRQ_CPU_CNTRL = (1 << 20),
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MVS_IRQ_GPIO = (1 << 21),
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MVS_IRQ_UART = (1 << 22),
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MVS_IRQ_SPI = (1 << 23),
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MVS_IRQ_I2C = (1 << 24),
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MVS_IRQ_SGPIO = (1 << 25),
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MVS_IRQ_COM_ERR = (1 << 29),
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MVS_IRQ_I2O_ERR = (1 << 30),
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MVS_IRQ_PCIE_ERR = (1 << 31),
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};
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union reg_phy_cfg {
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u32 v;
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struct {
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u32 phy_reset:1;
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u32 sas_support:1;
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u32 sata_support:1;
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u32 sata_host_mode:1;
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/*
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* bit 2: 6Gbps support
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* bit 1: 3Gbps support
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* bit 0: 1.5Gbps support
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*/
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u32 speed_support:3;
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u32 snw_3_support:1;
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u32 tx_lnk_parity:1;
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/*
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* bit 5: G1 (1.5Gbps) Without SSC
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* bit 4: G1 (1.5Gbps) with SSC
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* bit 3: G2 (3.0Gbps) Without SSC
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* bit 2: G2 (3.0Gbps) with SSC
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* bit 1: G3 (6.0Gbps) without SSC
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* bit 0: G3 (6.0Gbps) with SSC
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*/
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u32 tx_spt_phs_lnk_rate:6;
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/* 8h: 1.5Gbps 9h: 3Gbps Ah: 6Gbps */
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u32 tx_lgcl_lnk_rate:4;
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u32 tx_ssc_type:1;
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u32 sata_spin_up_spt:1;
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u32 sata_spin_up_en:1;
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u32 bypass_oob:1;
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u32 disable_phy:1;
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u32 rsvd:8;
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} u;
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};
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#define MAX_SG_ENTRY 255
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struct mvs_prd_imt {
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#ifndef __BIG_ENDIAN
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__le32 len:22;
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u8 _r_a:2;
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u8 misc_ctl:4;
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u8 inter_sel:4;
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#else
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u32 inter_sel:4;
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u32 misc_ctl:4;
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u32 _r_a:2;
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u32 len:22;
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#endif
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};
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struct mvs_prd {
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/* 64-bit buffer address */
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__le64 addr;
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/* 22-bit length */
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__le32 im_len;
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} __attribute__ ((packed));
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enum sgpio_registers {
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MVS_SGPIO_HOST_OFFSET = 0x100, /* offset between hosts */
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MVS_SGPIO_CFG0 = 0xc200,
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MVS_SGPIO_CFG0_ENABLE = (1 << 0), /* enable pins */
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MVS_SGPIO_CFG0_BLINKB = (1 << 1), /* blink generators */
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MVS_SGPIO_CFG0_BLINKA = (1 << 2),
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MVS_SGPIO_CFG0_INVSCLK = (1 << 3), /* invert signal? */
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MVS_SGPIO_CFG0_INVSLOAD = (1 << 4),
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MVS_SGPIO_CFG0_INVSDOUT = (1 << 5),
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MVS_SGPIO_CFG0_SLOAD_FALLEDGE = (1 << 6), /* rise/fall edge? */
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MVS_SGPIO_CFG0_SDOUT_FALLEDGE = (1 << 7),
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MVS_SGPIO_CFG0_SDIN_RISEEDGE = (1 << 8),
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MVS_SGPIO_CFG0_MAN_BITLEN_SHIFT = 18, /* bits/frame manual mode */
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MVS_SGPIO_CFG0_AUT_BITLEN_SHIFT = 24, /* bits/frame auto mode */
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MVS_SGPIO_CFG1 = 0xc204, /* blink timing register */
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MVS_SGPIO_CFG1_LOWA_SHIFT = 0, /* A off time */
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MVS_SGPIO_CFG1_HIA_SHIFT = 4, /* A on time */
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MVS_SGPIO_CFG1_LOWB_SHIFT = 8, /* B off time */
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MVS_SGPIO_CFG1_HIB_SHIFT = 12, /* B on time */
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MVS_SGPIO_CFG1_MAXACTON_SHIFT = 16, /* max activity on time */
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/* force activity off time */
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MVS_SGPIO_CFG1_FORCEACTOFF_SHIFT = 20,
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/* stretch activity on time */
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MVS_SGPIO_CFG1_STRCHACTON_SHIFT = 24,
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/* stretch activiity off time */
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MVS_SGPIO_CFG1_STRCHACTOFF_SHIFT = 28,
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MVS_SGPIO_CFG2 = 0xc208, /* clock speed register */
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MVS_SGPIO_CFG2_CLK_SHIFT = 0,
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MVS_SGPIO_CFG2_BLINK_SHIFT = 20,
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MVS_SGPIO_CTRL = 0xc20c, /* SDOUT/SDIN mode control */
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MVS_SGPIO_CTRL_SDOUT_AUTO = 2,
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MVS_SGPIO_CTRL_SDOUT_SHIFT = 2,
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MVS_SGPIO_DSRC = 0xc220, /* map ODn bits to drives */
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MVS_SGPIO_DCTRL = 0xc238,
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MVS_SGPIO_DCTRL_ERR_SHIFT = 0,
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MVS_SGPIO_DCTRL_LOC_SHIFT = 3,
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MVS_SGPIO_DCTRL_ACT_SHIFT = 5,
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};
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enum sgpio_led_status {
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LED_OFF = 0,
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LED_ON = 1,
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LED_BLINKA = 2,
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LED_BLINKA_INV = 3,
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LED_BLINKA_SOF = 4,
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LED_BLINKA_EOF = 5,
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LED_BLINKB = 6,
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LED_BLINKB_INV = 7,
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};
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#define DEFAULT_SGPIO_BITS ((LED_BLINKA_SOF << \
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MVS_SGPIO_DCTRL_ACT_SHIFT) << (8 * 3) | \
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(LED_BLINKA_SOF << \
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MVS_SGPIO_DCTRL_ACT_SHIFT) << (8 * 2) | \
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(LED_BLINKA_SOF << \
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MVS_SGPIO_DCTRL_ACT_SHIFT) << (8 * 1) | \
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(LED_BLINKA_SOF << \
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MVS_SGPIO_DCTRL_ACT_SHIFT) << (8 * 0))
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/*
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* these registers are accessed through port vendor
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* specific address/data registers
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*/
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enum sas_sata_phy_regs {
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GENERATION_1_SETTING = 0x118,
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GENERATION_1_2_SETTING = 0x11C,
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GENERATION_2_3_SETTING = 0x120,
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GENERATION_3_4_SETTING = 0x124,
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};
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#define SPI_CTRL_REG_94XX 0xc800
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#define SPI_ADDR_REG_94XX 0xc804
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#define SPI_WR_DATA_REG_94XX 0xc808
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#define SPI_RD_DATA_REG_94XX 0xc80c
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#define SPI_CTRL_READ_94XX (1U << 2)
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#define SPI_ADDR_VLD_94XX (1U << 1)
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#define SPI_CTRL_SpiStart_94XX (1U << 0)
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static inline int
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mv_ffc64(u64 v)
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{
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u64 x = ~v;
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return x ? __ffs64(x) : -1;
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}
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#define r_reg_set_enable(i) \
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(((i) > 31) ? mr32(MVS_STP_REG_SET_1) : \
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mr32(MVS_STP_REG_SET_0))
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#define w_reg_set_enable(i, tmp) \
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(((i) > 31) ? mw32(MVS_STP_REG_SET_1, tmp) : \
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mw32(MVS_STP_REG_SET_0, tmp))
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extern const struct mvs_dispatch mvs_94xx_dispatch;
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#endif
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