kernel_samsung_a34x-permissive/arch/arm/boot/dts/armada-xp-gp.dts

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Marvell Armada XP development board
 * (DB-MV784MP-GP)
 *
 * Copyright (C) 2013-2014 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * Note: this Device Tree assumes that the bootloader has remapped the
 * internal registers to 0xf1000000 (instead of the default
 * 0xd0000000). The 0xf1000000 is the default used by the recent,
 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
 * boards were delivered with an older version of the bootloader that
 * left internal registers mapped at 0xd0000000. If you are in this
 * situation, you should either update your bootloader (preferred
 * solution) or the below Device Tree should be adjusted.
 */

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "armada-xp-mv78460.dtsi"

/ {
	model = "Marvell Armada XP Development Board DB-MV784MP-GP";
	compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		/*
                 * 8 GB of plug-in RAM modules by default.The amount
                 * of memory available can be changed by the
                 * bootloader according the size of the module
                 * actually plugged. However, memory between
                 * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
                 * the address range used for I/O (internal registers,
                 * MBus windows).
		 */
		reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
		      <0x00000001 0x00000000 0x00000001 0x00000000>;
	};

	cpus {
		pm_pic {
			ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
				     <&gpio0 17 GPIO_ACTIVE_LOW>,
				     <&gpio0 18 GPIO_ACTIVE_LOW>;
		};
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
			  MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
			  MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
			  MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
			  MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;

		devbus-bootcs {
			status = "okay";

			/* Device Bus parameters are required */

			/* Read parameters */
			devbus,bus-width    = <16>;
			devbus,turn-off-ps  = <60000>;
			devbus,badr-skew-ps = <0>;
			devbus,acc-first-ps = <124000>;
			devbus,acc-next-ps  = <248000>;
			devbus,rd-setup-ps  = <0>;
			devbus,rd-hold-ps   = <0>;

			/* Write parameters */
			devbus,sync-enable = <0>;
			devbus,wr-high-ps  = <60000>;
			devbus,wr-low-ps   = <60000>;
			devbus,ale-wr-ps   = <60000>;

			/* NOR 16 MiB */
			nor@0 {
				compatible = "cfi-flash";
				reg = <0 0x1000000>;
				bank-width = <2>;
			};
		};

		internal-regs {
			serial@12000 {
				status = "okay";
			};
			serial@12100 {
				status = "okay";
			};
			serial@12200 {
				status = "okay";
			};
			serial@12300 {
				status = "okay";
			};
			pinctrl {
				pinctrl-0 = <&pic_pins>;
				pinctrl-names = "default";
				pic_pins: pic-pins-0 {
					marvell,pins = "mpp16", "mpp17",
						       "mpp18";
					marvell,function = "gpio";
				};
			};
			sata@a0000 {
				nr-ports = <2>;
				status = "okay";
			};

			ethernet@70000 {
				status = "okay";
				phy = <&phy0>;
				phy-mode = "qsgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <0>;
			};
			ethernet@74000 {
				status = "okay";
				phy = <&phy1>;
				phy-mode = "qsgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <1>;
			};
			ethernet@30000 {
				status = "okay";
				phy = <&phy2>;
				phy-mode = "qsgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <2>;
			};
			ethernet@34000 {
				status = "okay";
				phy = <&phy3>;
				phy-mode = "qsgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <3>;
			};

			/* Front-side USB slot */
			usb@50000 {
				status = "okay";
			};

			/* Back-side USB slot */
			usb@51000 {
				status = "okay";
			};

			bm@c0000 {
				status = "okay";
			};

			nand-controller@d0000 {
				status = "okay";

				nand@0 {
					reg = <0>;
					label = "pxa3xx_nand-0";
					nand-rb = <0>;
					nand-on-flash-bbt;
				};
			};
		};

		bm-bppi {
			status = "okay";
		};
	};
};

&pciec {
	status = "okay";

	/*
	 * The 3 slots are physically present as
	 * standard PCIe slots on the board.
	 */
	pcie@1,0 {
		/* Port 0, Lane 0 */
		status = "okay";
	};
	pcie@9,0 {
		/* Port 2, Lane 0 */
		status = "okay";
	};
	pcie@a,0 {
		/* Port 3, Lane 0 */
		status = "okay";
	};
};

&mdio {
	phy0: ethernet-phy@0 {
		reg = <16>;
	};

	phy1: ethernet-phy@1 {
		reg = <17>;
	};

	phy2: ethernet-phy@2 {
		reg = <18>;
	};

	phy3: ethernet-phy@3 {
		reg = <19>;
	};
};

&spi0 {
	status = "okay";

	spi-flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "n25q128a13", "jedec,spi-nor";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <108000000>;
	};
};