115 lines
1.7 KiB
Plaintext
115 lines
1.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2015 Andrea Merello <adnrea.merello@gmail.com>
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* Copyright (C) 2017 Alexander Graf <agraf@suse.de>
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*
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* Based on zynq-zed.dts which is:
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* Copyright (C) 2011 - 2014 Xilinx
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* Copyright (C) 2012 National Instruments Corp.
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*
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*/
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/dts-v1/;
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/include/ "zynq-7000.dtsi"
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/ {
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model = "Zynq Z-Turn MYIR Board";
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compatible = "myir,zynq-zturn", "xlnx,zynq-7000";
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aliases {
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ethernet0 = &gem0;
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serial0 = &uart1;
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serial1 = &uart0;
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mmc0 = &sdhci0;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x40000000>;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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gpio-leds {
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compatible = "gpio-leds";
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usr-led1 {
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label = "usr-led1";
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gpios = <&gpio0 0x0 0x1>;
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default-state = "off";
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};
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usr-led2 {
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label = "usr-led2";
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gpios = <&gpio0 0x9 0x1>;
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default-state = "off";
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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autorepeat;
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K1 {
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label = "K1";
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gpios = <&gpio0 0x32 0x1>;
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linux,code = <0x66>;
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gpio-key,wakeup;
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autorepeat;
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};
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};
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};
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&clkc {
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ps-clk-frequency = <33333333>;
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};
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&gem0 {
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status = "okay";
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phy-mode = "rgmii-id";
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phy-handle = <ðernet_phy>;
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ethernet_phy: ethernet-phy@0 {
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reg = <0x0>;
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};
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};
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&sdhci0 {
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status = "okay";
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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dr_mode = "host";
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};
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&can0 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <400000>;
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stlm75@49 {
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status = "okay";
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compatible = "lm75";
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reg = <0x49>;
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};
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accelerometer@53 {
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compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x";
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reg = <0x53>;
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interrupt-parent = <&intc>;
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interrupts = <0x0 0x1e 0x4>;
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};
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};
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