80 lines
1.9 KiB
ArmAsm
80 lines
1.9 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 1999-2002 Hewlett-Packard Co
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* Stephane Eranian <eranian@hpl.hp.com>
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* David Mosberger-Tang <davidm@hpl.hp.com>
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* Copyright (C) 2002 Ken Chen <kenneth.w.chen@intel.com>
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*
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* 1/06/01 davidm Tuned for Itanium.
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* 2/12/02 kchen Tuned for both Itanium and McKinley
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* 3/08/02 davidm Some more tweaking
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*/
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#include <asm/asmmacro.h>
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#include <asm/page.h>
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#include <asm/export.h>
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#ifdef CONFIG_ITANIUM
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# define L3_LINE_SIZE 64 // Itanium L3 line size
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# define PREFETCH_LINES 9 // magic number
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#else
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# define L3_LINE_SIZE 128 // McKinley L3 line size
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# define PREFETCH_LINES 12 // magic number
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#endif
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#define saved_lc r2
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#define dst_fetch r3
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#define dst1 r8
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#define dst2 r9
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#define dst3 r10
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#define dst4 r11
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#define dst_last r31
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GLOBAL_ENTRY(clear_page)
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.prologue
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.regstk 1,0,0,0
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mov r16 = PAGE_SIZE/L3_LINE_SIZE-1 // main loop count, -1=repeat/until
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.save ar.lc, saved_lc
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mov saved_lc = ar.lc
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.body
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mov ar.lc = (PREFETCH_LINES - 1)
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mov dst_fetch = in0
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adds dst1 = 16, in0
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adds dst2 = 32, in0
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;;
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.fetch: stf.spill.nta [dst_fetch] = f0, L3_LINE_SIZE
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adds dst3 = 48, in0 // executing this multiple times is harmless
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br.cloop.sptk.few .fetch
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;;
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addl dst_last = (PAGE_SIZE - PREFETCH_LINES*L3_LINE_SIZE), dst_fetch
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mov ar.lc = r16 // one L3 line per iteration
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adds dst4 = 64, in0
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;;
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#ifdef CONFIG_ITANIUM
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// Optimized for Itanium
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1: stf.spill.nta [dst1] = f0, 64
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stf.spill.nta [dst2] = f0, 64
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cmp.lt p8,p0=dst_fetch, dst_last
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;;
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#else
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// Optimized for McKinley
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1: stf.spill.nta [dst1] = f0, 64
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stf.spill.nta [dst2] = f0, 64
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stf.spill.nta [dst3] = f0, 64
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stf.spill.nta [dst4] = f0, 128
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cmp.lt p8,p0=dst_fetch, dst_last
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;;
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stf.spill.nta [dst1] = f0, 64
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stf.spill.nta [dst2] = f0, 64
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#endif
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stf.spill.nta [dst3] = f0, 64
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(p8) stf.spill.nta [dst_fetch] = f0, L3_LINE_SIZE
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br.cloop.sptk.few 1b
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;;
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mov ar.lc = saved_lc // restore lc
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br.ret.sptk.many rp
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END(clear_page)
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EXPORT_SYMBOL(clear_page)
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