252 lines
6.7 KiB
C
252 lines
6.7 KiB
C
/*
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* Interrupt handling for GE FPGA based PIC
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*
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* Author: Martyn Welch <martyn.welch@ge.com>
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*
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* 2008 (c) GE Intelligent Platforms Embedded Systems, Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <asm/byteorder.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/irq.h>
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#include "ge_pic.h"
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#define DEBUG
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt...) do { printk(KERN_DEBUG "gef_pic: " fmt); } while (0)
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#else
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#define DBG(fmt...) do { } while (0)
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#endif
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#define GEF_PIC_NUM_IRQS 32
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/* Interrupt Controller Interface Registers */
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#define GEF_PIC_INTR_STATUS 0x0000
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#define GEF_PIC_INTR_MASK(cpu) (0x0010 + (0x4 * cpu))
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#define GEF_PIC_CPU0_INTR_MASK GEF_PIC_INTR_MASK(0)
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#define GEF_PIC_CPU1_INTR_MASK GEF_PIC_INTR_MASK(1)
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#define GEF_PIC_MCP_MASK(cpu) (0x0018 + (0x4 * cpu))
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#define GEF_PIC_CPU0_MCP_MASK GEF_PIC_MCP_MASK(0)
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#define GEF_PIC_CPU1_MCP_MASK GEF_PIC_MCP_MASK(1)
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static DEFINE_RAW_SPINLOCK(gef_pic_lock);
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static void __iomem *gef_pic_irq_reg_base;
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static struct irq_domain *gef_pic_irq_host;
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static int gef_pic_cascade_irq;
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/*
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* Interrupt Controller Handling
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*
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* The interrupt controller handles interrupts for most on board interrupts,
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* apart from PCI interrupts. For example on SBC610:
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*
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* 17:31 RO Reserved
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* 16 RO PCI Express Doorbell 3 Status
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* 15 RO PCI Express Doorbell 2 Status
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* 14 RO PCI Express Doorbell 1 Status
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* 13 RO PCI Express Doorbell 0 Status
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* 12 RO Real Time Clock Interrupt Status
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* 11 RO Temperature Interrupt Status
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* 10 RO Temperature Critical Interrupt Status
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* 9 RO Ethernet PHY1 Interrupt Status
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* 8 RO Ethernet PHY3 Interrupt Status
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* 7 RO PEX8548 Interrupt Status
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* 6 RO Reserved
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* 5 RO Watchdog 0 Interrupt Status
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* 4 RO Watchdog 1 Interrupt Status
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* 3 RO AXIS Message FIFO A Interrupt Status
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* 2 RO AXIS Message FIFO B Interrupt Status
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* 1 RO AXIS Message FIFO C Interrupt Status
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* 0 RO AXIS Message FIFO D Interrupt Status
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*
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* Interrupts can be forwarded to one of two output lines. Nothing
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* clever is done, so if the masks are incorrectly set, a single input
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* interrupt could generate interrupts on both output lines!
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*
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* The dual lines are there to allow the chained interrupts to be easily
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* passed into two different cores. We currently do not use this functionality
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* in this driver.
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*
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* Controller can also be configured to generate Machine checks (MCP), again on
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* two lines, to be attached to two different cores. It is suggested that these
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* should be masked out.
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*/
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static void gef_pic_cascade(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned int cascade_irq;
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/*
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* See if we actually have an interrupt, call generic handling code if
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* we do.
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*/
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cascade_irq = gef_pic_get_irq();
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if (cascade_irq)
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generic_handle_irq(cascade_irq);
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chip->irq_eoi(&desc->irq_data);
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}
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static void gef_pic_mask(struct irq_data *d)
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{
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unsigned long flags;
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unsigned int hwirq = irqd_to_hwirq(d);
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u32 mask;
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raw_spin_lock_irqsave(&gef_pic_lock, flags);
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mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
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mask &= ~(1 << hwirq);
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out_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0), mask);
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raw_spin_unlock_irqrestore(&gef_pic_lock, flags);
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}
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static void gef_pic_mask_ack(struct irq_data *d)
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{
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/* Don't think we actually have to do anything to ack an interrupt,
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* we just need to clear down the devices interrupt and it will go away
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*/
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gef_pic_mask(d);
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}
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static void gef_pic_unmask(struct irq_data *d)
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{
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unsigned long flags;
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unsigned int hwirq = irqd_to_hwirq(d);
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u32 mask;
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raw_spin_lock_irqsave(&gef_pic_lock, flags);
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mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
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mask |= (1 << hwirq);
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out_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0), mask);
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raw_spin_unlock_irqrestore(&gef_pic_lock, flags);
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}
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static struct irq_chip gef_pic_chip = {
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.name = "gefp",
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.irq_mask = gef_pic_mask,
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.irq_mask_ack = gef_pic_mask_ack,
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.irq_unmask = gef_pic_unmask,
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};
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/* When an interrupt is being configured, this call allows some flexibilty
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* in deciding which irq_chip structure is used
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*/
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static int gef_pic_host_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hwirq)
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{
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/* All interrupts are LEVEL sensitive */
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irq_set_status_flags(virq, IRQ_LEVEL);
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irq_set_chip_and_handler(virq, &gef_pic_chip, handle_level_irq);
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return 0;
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}
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static int gef_pic_host_xlate(struct irq_domain *h, struct device_node *ct,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_flags)
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{
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*out_hwirq = intspec[0];
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if (intsize > 1)
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*out_flags = intspec[1];
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else
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*out_flags = IRQ_TYPE_LEVEL_HIGH;
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return 0;
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}
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static const struct irq_domain_ops gef_pic_host_ops = {
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.map = gef_pic_host_map,
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.xlate = gef_pic_host_xlate,
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};
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/*
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* Initialisation of PIC, this should be called in BSP
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*/
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void __init gef_pic_init(struct device_node *np)
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{
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unsigned long flags;
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/* Map the devices registers into memory */
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gef_pic_irq_reg_base = of_iomap(np, 0);
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raw_spin_lock_irqsave(&gef_pic_lock, flags);
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/* Initialise everything as masked. */
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out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU0_INTR_MASK, 0);
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out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU1_INTR_MASK, 0);
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out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU0_MCP_MASK, 0);
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out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU1_MCP_MASK, 0);
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raw_spin_unlock_irqrestore(&gef_pic_lock, flags);
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/* Map controller */
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gef_pic_cascade_irq = irq_of_parse_and_map(np, 0);
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if (!gef_pic_cascade_irq) {
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printk(KERN_ERR "SBC610: failed to map cascade interrupt");
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return;
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}
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/* Setup an irq_domain structure */
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gef_pic_irq_host = irq_domain_add_linear(np, GEF_PIC_NUM_IRQS,
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&gef_pic_host_ops, NULL);
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if (gef_pic_irq_host == NULL)
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return;
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/* Chain with parent controller */
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irq_set_chained_handler(gef_pic_cascade_irq, gef_pic_cascade);
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}
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/*
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* This is called when we receive an interrupt with apparently comes from this
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* chip - check, returning the highest interrupt generated or return 0.
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*/
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unsigned int gef_pic_get_irq(void)
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{
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u32 cause, mask, active;
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unsigned int virq = 0;
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int hwirq;
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cause = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_STATUS);
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mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
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active = cause & mask;
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if (active) {
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for (hwirq = GEF_PIC_NUM_IRQS - 1; hwirq > -1; hwirq--) {
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if (active & (0x1 << hwirq))
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break;
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}
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virq = irq_linear_revmap(gef_pic_irq_host,
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(irq_hw_number_t)hwirq);
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}
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return virq;
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}
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