142 lines
3.4 KiB
C
142 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Intel Transactional Synchronization Extensions (TSX) control.
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*
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* Copyright (C) 2019 Intel Corporation
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*
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* Author:
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* Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
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*/
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#include <linux/cpufeature.h>
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#include <asm/cmdline.h>
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#include "cpu.h"
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enum tsx_ctrl_states tsx_ctrl_state __ro_after_init = TSX_CTRL_NOT_SUPPORTED;
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void tsx_disable(void)
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{
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u64 tsx;
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rdmsrl(MSR_IA32_TSX_CTRL, tsx);
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/* Force all transactions to immediately abort */
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tsx |= TSX_CTRL_RTM_DISABLE;
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/*
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* Ensure TSX support is not enumerated in CPUID.
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* This is visible to userspace and will ensure they
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* do not waste resources trying TSX transactions that
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* will always abort.
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*/
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tsx |= TSX_CTRL_CPUID_CLEAR;
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wrmsrl(MSR_IA32_TSX_CTRL, tsx);
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}
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void tsx_enable(void)
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{
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u64 tsx;
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rdmsrl(MSR_IA32_TSX_CTRL, tsx);
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/* Enable the RTM feature in the cpu */
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tsx &= ~TSX_CTRL_RTM_DISABLE;
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/*
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* Ensure TSX support is enumerated in CPUID.
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* This is visible to userspace and will ensure they
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* can enumerate and use the TSX feature.
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*/
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tsx &= ~TSX_CTRL_CPUID_CLEAR;
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wrmsrl(MSR_IA32_TSX_CTRL, tsx);
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}
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static bool __init tsx_ctrl_is_supported(void)
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{
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u64 ia32_cap = x86_read_arch_cap_msr();
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/*
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* TSX is controlled via MSR_IA32_TSX_CTRL. However, support for this
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* MSR is enumerated by ARCH_CAP_TSX_MSR bit in MSR_IA32_ARCH_CAPABILITIES.
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*
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* TSX control (aka MSR_IA32_TSX_CTRL) is only available after a
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* microcode update on CPUs that have their MSR_IA32_ARCH_CAPABILITIES
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* bit MDS_NO=1. CPUs with MDS_NO=0 are not planned to get
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* MSR_IA32_TSX_CTRL support even after a microcode update. Thus,
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* tsx= cmdline requests will do nothing on CPUs without
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* MSR_IA32_TSX_CTRL support.
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*/
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return !!(ia32_cap & ARCH_CAP_TSX_CTRL_MSR);
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}
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static enum tsx_ctrl_states x86_get_tsx_auto_mode(void)
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{
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if (boot_cpu_has_bug(X86_BUG_TAA))
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return TSX_CTRL_DISABLE;
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return TSX_CTRL_ENABLE;
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}
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void __init tsx_init(void)
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{
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char arg[5] = {};
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int ret;
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if (!tsx_ctrl_is_supported())
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return;
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ret = cmdline_find_option(boot_command_line, "tsx", arg, sizeof(arg));
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if (ret >= 0) {
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if (!strcmp(arg, "on")) {
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tsx_ctrl_state = TSX_CTRL_ENABLE;
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} else if (!strcmp(arg, "off")) {
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tsx_ctrl_state = TSX_CTRL_DISABLE;
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} else if (!strcmp(arg, "auto")) {
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tsx_ctrl_state = x86_get_tsx_auto_mode();
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} else {
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tsx_ctrl_state = TSX_CTRL_DISABLE;
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pr_err("tsx: invalid option, defaulting to off\n");
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}
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} else {
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/* tsx= not provided */
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if (IS_ENABLED(CONFIG_X86_INTEL_TSX_MODE_AUTO))
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tsx_ctrl_state = x86_get_tsx_auto_mode();
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else if (IS_ENABLED(CONFIG_X86_INTEL_TSX_MODE_OFF))
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tsx_ctrl_state = TSX_CTRL_DISABLE;
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else
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tsx_ctrl_state = TSX_CTRL_ENABLE;
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}
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if (tsx_ctrl_state == TSX_CTRL_DISABLE) {
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tsx_disable();
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/*
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* tsx_disable() will change the state of the RTM and HLE CPUID
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* bits. Clear them here since they are now expected to be not
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* set.
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*/
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setup_clear_cpu_cap(X86_FEATURE_RTM);
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setup_clear_cpu_cap(X86_FEATURE_HLE);
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} else if (tsx_ctrl_state == TSX_CTRL_ENABLE) {
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/*
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* HW defaults TSX to be enabled at bootup.
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* We may still need the TSX enable support
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* during init for special cases like
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* kexec after TSX is disabled.
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*/
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tsx_enable();
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/*
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* tsx_enable() will change the state of the RTM and HLE CPUID
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* bits. Force them here since they are now expected to be set.
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*/
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setup_force_cpu_cap(X86_FEATURE_RTM);
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setup_force_cpu_cap(X86_FEATURE_HLE);
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}
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}
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