6db4831e98
Android 14
96 lines
2 KiB
C
96 lines
2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Sean Wang <sean.wang@mediatek.com>
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*
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt2701-clk.h>
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#define GATE_G3D(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &g3d_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate_regs g3d_cg_regs = {
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.sta_ofs = 0x0,
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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};
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static const struct mtk_gate g3d_clks[] = {
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GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
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};
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static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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int r;
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clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
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mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks),
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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dev_err(&pdev->dev,
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"could not register clock provider: %s: %d\n",
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pdev->name, r);
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mtk_register_reset_controller(node, 1, 0xc);
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return r;
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}
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static const struct of_device_id of_match_clk_mt2701_g3d[] = {
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{
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.compatible = "mediatek,mt2701-g3dsys",
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.data = clk_mt2701_g3dsys_init,
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}, {
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/* sentinel */
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}
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};
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static int clk_mt2701_g3d_probe(struct platform_device *pdev)
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{
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int (*clk_init)(struct platform_device *);
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int r;
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clk_init = of_device_get_match_data(&pdev->dev);
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if (!clk_init)
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return -EINVAL;
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r = clk_init(pdev);
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if (r)
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dev_err(&pdev->dev,
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"could not register clock provider: %s: %d\n",
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pdev->name, r);
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return r;
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}
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static struct platform_driver clk_mt2701_g3d_drv = {
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.probe = clk_mt2701_g3d_probe,
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.driver = {
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.name = "clk-mt2701-g3d",
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.of_match_table = of_match_clk_mt2701_g3d,
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},
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};
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builtin_platform_driver(clk_mt2701_g3d_drv);
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