111 lines
2.9 KiB
C
111 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Wendell Lin <wendell.lin@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/mt6779-clk.h>
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#include <linux/slab.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#define MT_CLKMGR_MODULE_INIT 0
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#define CCF_SUBSYS_DEBUG 1
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static const struct mtk_gate_regs apumdla_cg_regs = {
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.set_ofs = 0x0004,
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.clr_ofs = 0x0008,
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.sta_ofs = 0x0000,
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};
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#define GATE_APU_MDLA_DUMMY(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &apumdla_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr_dummy, \
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}
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static const struct mtk_gate apumdla_clks[] = {
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GATE_APU_MDLA_DUMMY(CLK_APU_MDLA_B0, "mdla_b0", "dsp3_sel", 0),
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GATE_APU_MDLA_DUMMY(CLK_APU_MDLA_B1, "mdla_b1", "dsp3_sel", 1),
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GATE_APU_MDLA_DUMMY(CLK_APU_MDLA_B2, "mdla_b2", "dsp3_sel", 2),
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GATE_APU_MDLA_DUMMY(CLK_APU_MDLA_B3, "mdla_b3", "dsp3_sel", 3),
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GATE_APU_MDLA_DUMMY(CLK_APU_MDLA_B4, "mdla_b4", "dsp3_sel", 4),
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GATE_APU_MDLA_DUMMY(CLK_APU_MDLA_B5, "mdla_b5", "dsp3_sel", 5),
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GATE_APU_MDLA_DUMMY(CLK_APU_MDLA_B6, "mdla_b6", "dsp3_sel", 6),
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GATE_APU_MDLA_DUMMY(CLK_APU_MDLA_B7, "mdla_b7", "dsp3_sel", 7),
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GATE_APU_MDLA_DUMMY(CLK_APU_MDLA_B8, "mdla_b8", "dsp3_sel", 8),
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GATE_APU_MDLA_DUMMY(CLK_APU_MDLA_B9, "mdla_b9", "dsp3_sel", 9),
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GATE_APU_MDLA_DUMMY(CLK_APU_MDLA_B10, "mdla_b10", "dsp3_sel", 10),
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GATE_APU_MDLA_DUMMY(CLK_APU_MDLA_B11, "mdla_b11", "dsp3_sel", 11),
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GATE_APU_MDLA_DUMMY(CLK_APU_MDLA_B12, "mdla_b12", "dsp3_sel", 12),
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GATE_APU_MDLA_DUMMY(CLK_APU_MDLA_APB, "mdla_apb", "dsp3_sel", 13),
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};
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static const struct of_device_id of_match_clk_mt6779_apumdla[] = {
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{ .compatible = "mediatek,mt6779-apu_mdla", },
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{}
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};
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static int clk_mt6779_apumdla_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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int ret;
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clk_data = mtk_alloc_clk_data(CLK_APU_MDLA_NR_CLK);
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if (!clk_data) {
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pr_notice("%s(): alloc clk data failed!\n", __func__);
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return -ENOMEM;
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}
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#if CCF_SUBSYS_DEBUG
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pr_info("%s(): clk data number: %d\n", __func__, clk_data->clk_num);
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#endif
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mtk_clk_register_gates(node, apumdla_clks, ARRAY_SIZE(apumdla_clks),
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clk_data);
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ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (ret) {
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pr_notice("%s(): could not register clock provider: %d\n",
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__func__, ret);
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kfree(clk_data);
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}
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return ret;
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}
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static struct platform_driver clk_mt6779_apumdla_drv = {
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.probe = clk_mt6779_apumdla_probe,
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.driver = {
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.name = "clk-mt6779-apu_mdla",
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.of_match_table = of_match_clk_mt6779_apumdla,
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},
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};
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#if MT_CLKMGR_MODULE_INIT
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builtin_platform_driver(clk_mt6779_apumdla_drv);
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#else
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static int __init clk_mt6779_apumdla_platform_init(void)
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{
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return platform_driver_register(&clk_mt6779_apumdla_drv);
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}
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arch_initcall_sync(clk_mt6779_apumdla_platform_init);
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#endif /* MT_CLKMGR_MODULE_INIT */
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