182 lines
3.7 KiB
C
182 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __NITROX_DEV_H
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#define __NITROX_DEV_H
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#define VERSION_LEN 32
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struct nitrox_cmdq {
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/* command queue lock */
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spinlock_t cmdq_lock;
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/* response list lock */
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spinlock_t response_lock;
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/* backlog list lock */
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spinlock_t backlog_lock;
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/* request submitted to chip, in progress */
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struct list_head response_head;
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/* hw queue full, hold in backlog list */
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struct list_head backlog_head;
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/* doorbell address */
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u8 __iomem *dbell_csr_addr;
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/* base address of the queue */
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u8 *head;
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struct nitrox_device *ndev;
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/* flush pending backlog commands */
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struct work_struct backlog_qflush;
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/* requests posted waiting for completion */
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atomic_t pending_count;
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/* requests in backlog queues */
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atomic_t backlog_count;
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int write_idx;
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/* command size 32B/64B */
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u8 instr_size;
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u8 qno;
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u32 qsize;
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/* unaligned addresses */
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u8 *head_unaligned;
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dma_addr_t dma_unaligned;
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/* dma address of the base */
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dma_addr_t dma;
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};
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struct nitrox_hw {
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/* firmware version */
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char fw_name[VERSION_LEN];
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u16 vendor_id;
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u16 device_id;
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u8 revision_id;
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/* CNN55XX cores */
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u8 se_cores;
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u8 ae_cores;
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u8 zip_cores;
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};
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#define MAX_MSIX_VECTOR_NAME 20
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/**
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* vectors for queues (64 AE, 64 SE and 64 ZIP) and
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* error condition/mailbox.
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*/
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#define MAX_MSIX_VECTORS 192
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struct nitrox_msix {
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struct msix_entry *entries;
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char **names;
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DECLARE_BITMAP(irqs, MAX_MSIX_VECTORS);
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u32 nr_entries;
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};
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struct bh_data {
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/* slc port completion count address */
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u8 __iomem *completion_cnt_csr_addr;
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struct nitrox_cmdq *cmdq;
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struct tasklet_struct resp_handler;
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};
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struct nitrox_bh {
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struct bh_data *slc;
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};
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/* NITROX-V driver state */
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#define NITROX_UCODE_LOADED 0
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#define NITROX_READY 1
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/* command queue size */
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#define DEFAULT_CMD_QLEN 2048
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/* command timeout in milliseconds */
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#define CMD_TIMEOUT 2000
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#define DEV(ndev) ((struct device *)(&(ndev)->pdev->dev))
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#define PF_MODE 0
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#define NITROX_CSR_ADDR(ndev, offset) \
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((ndev)->bar_addr + (offset))
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/**
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* struct nitrox_device - NITROX Device Information.
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* @list: pointer to linked list of devices
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* @bar_addr: iomap address
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* @pdev: PCI device information
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* @status: NITROX status
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* @timeout: Request timeout in jiffies
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* @refcnt: Device usage count
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* @idx: device index (0..N)
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* @node: NUMA node id attached
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* @qlen: Command queue length
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* @nr_queues: Number of command queues
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* @ctx_pool: DMA pool for crypto context
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* @pkt_cmdqs: SE Command queues
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* @msix: MSI-X information
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* @bh: post processing work
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* @hw: hardware information
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* @debugfs_dir: debugfs directory
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*/
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struct nitrox_device {
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struct list_head list;
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u8 __iomem *bar_addr;
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struct pci_dev *pdev;
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unsigned long status;
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unsigned long timeout;
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refcount_t refcnt;
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u8 idx;
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int node;
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u16 qlen;
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u16 nr_queues;
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struct dma_pool *ctx_pool;
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struct nitrox_cmdq *pkt_cmdqs;
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struct nitrox_msix msix;
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struct nitrox_bh bh;
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struct nitrox_hw hw;
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#if IS_ENABLED(CONFIG_DEBUG_FS)
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struct dentry *debugfs_dir;
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#endif
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};
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/**
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* nitrox_read_csr - Read from device register
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* @ndev: NITROX device
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* @offset: offset of the register to read
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*
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* Returns: value read
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*/
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static inline u64 nitrox_read_csr(struct nitrox_device *ndev, u64 offset)
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{
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return readq(ndev->bar_addr + offset);
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}
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/**
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* nitrox_write_csr - Write to device register
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* @ndev: NITROX device
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* @offset: offset of the register to write
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* @value: value to write
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*/
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static inline void nitrox_write_csr(struct nitrox_device *ndev, u64 offset,
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u64 value)
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{
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writeq(value, (ndev->bar_addr + offset));
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}
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static inline int nitrox_ready(struct nitrox_device *ndev)
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{
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return test_bit(NITROX_READY, &ndev->status);
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}
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#endif /* __NITROX_DEV_H */
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