189 lines
6 KiB
C
189 lines
6 KiB
C
/*******************************************************************************
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*
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* Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenFabrics.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*******************************************************************************/
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#ifndef I40IW_PUDA_H
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#define I40IW_PUDA_H
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#define I40IW_IEQ_MPA_FRAMING 6
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struct i40iw_sc_dev;
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struct i40iw_sc_qp;
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struct i40iw_sc_cq;
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enum puda_resource_type {
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I40IW_PUDA_RSRC_TYPE_ILQ = 1,
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I40IW_PUDA_RSRC_TYPE_IEQ
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};
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enum puda_rsrc_complete {
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PUDA_CQ_CREATED = 1,
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PUDA_QP_CREATED,
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PUDA_TX_COMPLETE,
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PUDA_RX_COMPLETE,
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PUDA_HASH_CRC_COMPLETE
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};
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struct i40iw_puda_completion_info {
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struct i40iw_qp_uk *qp;
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u8 q_type;
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u8 vlan_valid;
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u8 l3proto;
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u8 l4proto;
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u16 payload_len;
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u32 compl_error; /* No_err=0, else major and minor err code */
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u32 qp_id;
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u32 wqe_idx;
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};
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struct i40iw_puda_send_info {
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u64 paddr; /* Physical address */
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u32 len;
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u8 tcplen;
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u8 maclen;
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bool ipv4;
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bool doloopback;
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void *scratch;
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};
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struct i40iw_puda_buf {
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struct list_head list; /* MUST be first entry */
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struct i40iw_dma_mem mem; /* DMA memory for the buffer */
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struct i40iw_puda_buf *next; /* for alloclist in rsrc struct */
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struct i40iw_virt_mem buf_mem; /* Buffer memory for this buffer */
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void *scratch;
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u8 *iph;
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u8 *tcph;
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u8 *data;
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u16 datalen;
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u16 vlan_id;
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u8 tcphlen; /* tcp length in bytes */
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u8 maclen; /* mac length in bytes */
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u32 totallen; /* machlen+iphlen+tcphlen+datalen */
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atomic_t refcount;
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u8 hdrlen;
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bool ipv4;
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u32 seqnum;
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};
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struct i40iw_puda_rsrc_info {
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enum puda_resource_type type; /* ILQ or IEQ */
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u32 count;
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u16 pd_id;
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u32 cq_id;
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u32 qp_id;
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u32 sq_size;
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u32 rq_size;
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u16 buf_size;
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u16 mss;
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u32 tx_buf_cnt; /* total bufs allocated will be rq_size + tx_buf_cnt */
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void (*receive)(struct i40iw_sc_vsi *, struct i40iw_puda_buf *);
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void (*xmit_complete)(struct i40iw_sc_vsi *, void *);
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};
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struct i40iw_puda_rsrc {
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struct i40iw_sc_cq cq;
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struct i40iw_sc_qp qp;
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struct i40iw_sc_pd sc_pd;
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struct i40iw_sc_dev *dev;
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struct i40iw_sc_vsi *vsi;
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struct i40iw_dma_mem cqmem;
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struct i40iw_dma_mem qpmem;
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struct i40iw_virt_mem ilq_mem;
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enum puda_rsrc_complete completion;
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enum puda_resource_type type;
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u16 buf_size; /*buffer must be max datalen + tcpip hdr + mac */
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u16 mss;
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u32 cq_id;
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u32 qp_id;
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u32 sq_size;
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u32 rq_size;
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u32 cq_size;
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struct i40iw_sq_uk_wr_trk_info *sq_wrtrk_array;
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u64 *rq_wrid_array;
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u32 compl_rxwqe_idx;
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u32 rx_wqe_idx;
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u32 rxq_invalid_cnt;
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u32 tx_wqe_avail_cnt;
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bool check_crc;
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struct shash_desc *hash_desc;
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struct list_head txpend;
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struct list_head bufpool; /* free buffers pool list for recv and xmit */
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u32 alloc_buf_count;
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u32 avail_buf_count; /* snapshot of currently available buffers */
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spinlock_t bufpool_lock;
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struct i40iw_puda_buf *alloclist;
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void (*receive)(struct i40iw_sc_vsi *, struct i40iw_puda_buf *);
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void (*xmit_complete)(struct i40iw_sc_vsi *, void *);
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/* puda stats */
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u64 stats_buf_alloc_fail;
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u64 stats_pkt_rcvd;
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u64 stats_pkt_sent;
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u64 stats_rcvd_pkt_err;
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u64 stats_sent_pkt_q;
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u64 stats_bad_qp_id;
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};
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struct i40iw_puda_buf *i40iw_puda_get_bufpool(struct i40iw_puda_rsrc *rsrc);
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void i40iw_puda_ret_bufpool(struct i40iw_puda_rsrc *rsrc,
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struct i40iw_puda_buf *buf);
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void i40iw_puda_send_buf(struct i40iw_puda_rsrc *rsrc,
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struct i40iw_puda_buf *buf);
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enum i40iw_status_code i40iw_puda_send(struct i40iw_sc_qp *qp,
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struct i40iw_puda_send_info *info);
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enum i40iw_status_code i40iw_puda_create_rsrc(struct i40iw_sc_vsi *vsi,
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struct i40iw_puda_rsrc_info *info);
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void i40iw_puda_dele_resources(struct i40iw_sc_vsi *vsi,
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enum puda_resource_type type,
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bool reset);
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enum i40iw_status_code i40iw_puda_poll_completion(struct i40iw_sc_dev *dev,
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struct i40iw_sc_cq *cq, u32 *compl_err);
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struct i40iw_sc_qp *i40iw_ieq_get_qp(struct i40iw_sc_dev *dev,
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struct i40iw_puda_buf *buf);
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enum i40iw_status_code i40iw_puda_get_tcpip_info(struct i40iw_puda_completion_info *info,
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struct i40iw_puda_buf *buf);
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enum i40iw_status_code i40iw_ieq_check_mpacrc(struct shash_desc *desc,
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void *addr, u32 length, u32 value);
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enum i40iw_status_code i40iw_init_hash_desc(struct shash_desc **desc);
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void i40iw_ieq_mpa_crc_ae(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp);
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void i40iw_free_hash_desc(struct shash_desc *desc);
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void i40iw_ieq_update_tcpip_info(struct i40iw_puda_buf *buf, u16 length,
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u32 seqnum);
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enum i40iw_status_code i40iw_cqp_qp_create_cmd(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp);
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enum i40iw_status_code i40iw_cqp_cq_create_cmd(struct i40iw_sc_dev *dev, struct i40iw_sc_cq *cq);
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void i40iw_cqp_qp_destroy_cmd(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp);
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void i40iw_cqp_cq_destroy_cmd(struct i40iw_sc_dev *dev, struct i40iw_sc_cq *cq);
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void i40iw_ieq_cleanup_qp(struct i40iw_puda_rsrc *ieq, struct i40iw_sc_qp *qp);
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#endif
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