380 lines
10 KiB
C
380 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __PSEUDO_M4U_PORT_H__
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#define __PSEUDO_M4U_PORT_H__
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#include <linux/ioctl.h>
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#include <linux/fs.h>
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#include <linux/list.h>
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#ifdef CONFIG_ARM64
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#include <linux/iova.h>
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#endif
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#include <linux/iommu.h>
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#define M4U_PAGE_SIZE 0x1000
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#define M4U_GET_PAGE_NUM(va, size) \
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(((((unsigned long)va)&(M4U_PAGE_SIZE-1)) +\
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(size)+(M4U_PAGE_SIZE-1)) >> 12)
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#define NORMAL_M4U_NUMBER 1
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#define TOTAL_M4U_NUM 2
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#define M4U_REG_SIZE 0x5e0
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#define M4U_PORT_NR 28
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#define SMI_LARB_NR 9
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#define M4U_PAGE_MASK 0xfff
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/* public flags */
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/* engine access this buffer in sequncial way. */
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#define M4U_FLAGS_SEQ_ACCESS (1<<0)
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/* fix allocation, we will use mva user specified. */
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#define M4U_FLAGS_FIX_MVA (1<<1)
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#define M4U_FLAGS_SEC_SHAREABLE (1<<2) /* the mva will share in SWd */
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/* the allocator will search free mva from user specified. */
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#define M4U_FLAGS_START_FROM (1<<3)
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#define M4U_FLAGS_SG_READY (1<<4)
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/* optimized, recommand to use */
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enum M4U_CACHE_SYNC_ENUM {
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M4U_CACHE_CLEAN_BY_RANGE,
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M4U_CACHE_INVALID_BY_RANGE,
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M4U_CACHE_FLUSH_BY_RANGE,
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M4U_CACHE_CLEAN_ALL,
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M4U_CACHE_INVALID_ALL,
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M4U_CACHE_FLUSH_ALL,
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};
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/* port related: virtuality, security, distance */
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struct M4U_PORT_STRUCT {
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/*hardware port ID, defined in M4U_PORT_ID_ENUM*/
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int ePortID;
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unsigned int Virtuality;
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unsigned int Security;
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unsigned int domain; /*domain : 0 1 2 3*/
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unsigned int Distance;
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unsigned int Direction; /* 0:- 1:+*/
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};
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enum M4U_DMA_DIR_ENUM {
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M4U_DMA_READ_WRITE = 0,
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M4U_DMA_READ = 1,
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M4U_DMA_WRITE = 2,
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M4U_DMA_NONE_OP = 3,
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};
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/* module related: alloc/dealloc MVA buffer */
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struct M4U_MOUDLE_STRUCT {
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int port;
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unsigned long BufAddr;
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unsigned int BufSize;
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unsigned int prot;
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unsigned int MVAStart;
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unsigned int MVAEnd;
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unsigned int flags;
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};
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enum M4U_DMA_TYPE {
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M4U_DMA_MAP_AREA,
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M4U_DMA_UNMAP_AREA,
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M4U_DMA_FLUSH_BY_RANGE,
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};
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enum M4U_DMA_DIR {
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M4U_DMA_FROM_DEVICE,
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M4U_DMA_TO_DEVICE,
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M4U_DMA_BIDIRECTIONAL,
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};
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struct M4U_CACHE_STRUCT {
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int port;
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enum M4U_CACHE_SYNC_ENUM eCacheSync;
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unsigned long va;
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unsigned int size;
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unsigned int mva;
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};
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struct M4U_DMA_STRUCT {
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int port;
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enum M4U_DMA_TYPE eDMAType;
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enum M4U_DMA_DIR eDMADir;
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unsigned long va;
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unsigned int size;
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unsigned int mva;
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};
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struct M4U_PERF_COUNT {
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unsigned int transaction_cnt;
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unsigned int main_tlb_miss_cnt;
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unsigned int pfh_tlb_miss_cnt;
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unsigned int pfh_cnt;
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};
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struct mva_info_t {
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struct list_head link;
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unsigned long bufAddr;
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unsigned int mvaStart;
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unsigned int size;
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int eModuleId;
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unsigned int flags;
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int security;
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int cache_coherent;
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unsigned int mapped_kernel_va_for_debug;
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};
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struct m4u_buf_info_t {
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struct list_head link;
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unsigned long va;
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unsigned int mva;
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unsigned int size;
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int port;
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unsigned int prot;
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unsigned int flags;
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struct sg_table *sg_table;
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unsigned int mva_align;
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unsigned int size_align;
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int seq_id;
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unsigned long mapped_kernel_va_for_debug;
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};
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struct m4u_client_t {
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/* mutex to protect mvaList */
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/* should get this mutex whenever add/delete/interate mvaList */
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struct mutex dataMutex;
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pid_t open_pid;
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pid_t open_tgid;
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struct list_head mvaList;
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};
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struct port_mva_info_t {
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int emoduleid;
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unsigned long va;
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unsigned int buf_size;
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int security;
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int cache_coherent;
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unsigned int flags;
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unsigned int iova_start;
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unsigned int iova_end;
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unsigned int mva;
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};
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struct m4u_device {
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/*struct miscdevice dev;*/
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struct proc_dir_entry *m4u_dev_proc_entry;
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};
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/* we use this for trace the mva<-->sg_table relation ship */
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struct mva_sglist {
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struct list_head list;
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unsigned int mva;
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struct iova *iova;
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struct sg_table *table;
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};
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struct pseudo_device {
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struct device *dev; /* record the device for config mmu use. */
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int larbid; /* the larb id of this device*/
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bool mmuen; /* whether this larb have been configed or not. */
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};
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struct m4u_port_array {
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#define M4U_PORT_ATTR_EN (1<<0)
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#define M4U_PORT_ATTR_VIRTUAL (1<<1)
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#define M4U_PORT_ATTR_SEC (1<<2)
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unsigned char ports[M4U_PORT_NR];
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};
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extern unsigned long max_pfn;
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extern unsigned char *pMlock_cnt;
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extern unsigned int mlock_cnt_size;
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extern unsigned long pagetable_pa;
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#ifndef dmac_map_area
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#ifdef CONFIG_ARM64
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#define dmac_map_area __dma_map_area
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#else
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#define dmac_map_area v7_dma_map_area
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extern void dmac_map_area(const void *, size_t, int);
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#endif
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#endif
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#ifndef dmac_unmap_area
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#ifdef CONFIG_ARM64
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#define dmac_unmap_area __dma_unmap_area
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#else
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#define dmac_unmap_area v7_dma_unmap_area
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extern void dmac_unmap_area(const void *, size_t, int);
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#endif
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#endif
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#ifndef dmac_flush_range
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#define dmac_flush_range __dma_flush_range
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#endif
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/* function prototype */
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#ifndef outer_clean_all
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#define outer_clean_all(...)
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#endif
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#ifndef outer_flush_all
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#define outer_flush_all(...)
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#endif
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#ifndef IOVA_PFN
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#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
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#endif
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#if ((defined(CONFIG_MTK_IN_HOUSE_TEE_SUPPORT)) &&\
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(defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)))
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#define M4U_TEE_SERVICE_ENABLE
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#endif
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#ifdef M4U_TEE_SERVICE_ENABLE
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unsigned int mtk_init_tz_m4u(void);
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#endif
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int m4u_config_port(struct M4U_PORT_STRUCT *pM4uPort);
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struct device *m4u_get_larbdev(int portid);
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struct sg_table *m4u_find_sgtable(unsigned int mva);
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struct sg_table *m4u_del_sgtable(unsigned int mva);
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struct sg_table *m4u_add_sgtable(struct mva_sglist *mva_sg);
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int m4u_va_align(unsigned long *addr, unsigned int *size);
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int m4u_alloc_mva(int eModuleID,
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unsigned long BufAddr,
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unsigned int BufSize,
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int security, int cache_coherent, unsigned int *pRetMVABuf);
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/* struct sg_table *pseudo_get_sg(int portid, unsigned long va, int size); */
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struct sg_table *m4u_create_sgtable(unsigned long va, unsigned int size);
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int pseudo_alloc_mva(struct m4u_client_t *client, int port,
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unsigned long va, struct sg_table *sg_table,
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unsigned int size, unsigned int prot,
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unsigned int flags, unsigned int *pMva);
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int pseudo_dealloc_mva(struct m4u_client_t *client, int port,
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unsigned int mva);
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int __m4u_dealloc_mva(int eModuleID, const unsigned long BufAddr,
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const unsigned int BufSize, const unsigned int MVA,
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struct sg_table *sg_table);
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int m4u_dealloc_mva(int eModuleID,
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const unsigned long BufAddr, const unsigned int BufSize,
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const unsigned int MVA);
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int m4u_dealloc_mva_sg(int eModuleID,
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struct sg_table *sg_table,
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const unsigned int BufSize, const unsigned int MVA);
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int m4u_alloc_mva_sg(struct port_mva_info_t *port_info,
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struct sg_table *sg_table);
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int pseudo_config_port_tee(int kernelport);
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int m4u_mva_map_kernel(unsigned int mva,
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unsigned long size, unsigned long *map_va,
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unsigned int *map_size);
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int m4u_mva_unmap_kernel(unsigned int mva,
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unsigned long size, unsigned long map_va);
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extern void smp_inner_dcache_flush_all(void);
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extern phys_addr_t mtkfb_get_fb_base(void);
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extern size_t mtkfb_get_fb_size(void);
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#ifdef CONFIG_ARM64
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struct iova *__alloc_iova(struct iova_domain *iovad, size_t size,
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dma_addr_t dma_limit);
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void __free_iova(struct iova_domain *iovad, struct iova *iova);
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#endif
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void __iommu_dma_unmap(struct iommu_domain *domain, dma_addr_t dma_addr);
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static inline int mtk_smi_vp_setting(bool osd_4k)
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{
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return 0;
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}
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static inline int mtk_smi_init_setting(void)
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{
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return 0;
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}
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extern unsigned long mtk_get_pgt_base(void);
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bool m4u_portid_valid(const int portID);
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const char *m4u_get_port_name(const int portID);
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/* IOCTL commnad */
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#define MTK_M4U_MAGICNO 'g'
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#define MTK_M4U_T_POWER_ON _IOW(MTK_M4U_MAGICNO, 0, int)
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#define MTK_M4U_T_POWER_OFF _IOW(MTK_M4U_MAGICNO, 1, int)
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#define MTK_M4U_T_DUMP_REG _IOW(MTK_M4U_MAGICNO, 2, int)
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#define MTK_M4U_T_DUMP_INFO _IOW(MTK_M4U_MAGICNO, 3, int)
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#define MTK_M4U_T_ALLOC_MVA _IOWR(MTK_M4U_MAGICNO, 4, int)
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#define MTK_M4U_T_DEALLOC_MVA _IOW(MTK_M4U_MAGICNO, 5, int)
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#define MTK_M4U_T_INSERT_TLB_RANGE _IOW(MTK_M4U_MAGICNO, 6, int)
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#define MTK_M4U_T_INVALID_TLB_RANGE _IOW(MTK_M4U_MAGICNO, 7, int)
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#define MTK_M4U_T_INVALID_TLB_ALL _IOW(MTK_M4U_MAGICNO, 8, int)
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#define MTK_M4U_T_MANUAL_INSERT_ENTRY _IOW(MTK_M4U_MAGICNO, 9, int)
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#define MTK_M4U_T_CACHE_SYNC _IOW(MTK_M4U_MAGICNO, 10, int)
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#define MTK_M4U_T_CONFIG_PORT _IOW(MTK_M4U_MAGICNO, 11, int)
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#define MTK_M4U_T_CONFIG_ASSERT _IOW(MTK_M4U_MAGICNO, 12, int)
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#define MTK_M4U_T_INSERT_WRAP_RANGE _IOW(MTK_M4U_MAGICNO, 13, int)
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#define MTK_M4U_T_MONITOR_START _IOW(MTK_M4U_MAGICNO, 14, int)
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#define MTK_M4U_T_MONITOR_STOP _IOW(MTK_M4U_MAGICNO, 15, int)
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#define MTK_M4U_T_RESET_MVA_RELEASE_TLB _IOW(MTK_M4U_MAGICNO, 16, int)
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#define MTK_M4U_T_CONFIG_PORT_ROTATOR _IOW(MTK_M4U_MAGICNO, 17, int)
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#define MTK_M4U_T_QUERY_MVA _IOW(MTK_M4U_MAGICNO, 18, int)
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#define MTK_M4U_T_M4UDrv_CONSTRUCT _IOW(MTK_M4U_MAGICNO, 19, int)
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#define MTK_M4U_T_M4UDrv_DECONSTRUCT _IOW(MTK_M4U_MAGICNO, 20, int)
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#define MTK_M4U_T_DUMP_PAGETABLE _IOW(MTK_M4U_MAGICNO, 21, int)
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#define MTK_M4U_T_REGISTER_BUFFER _IOW(MTK_M4U_MAGICNO, 22, int)
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#define MTK_M4U_T_CACHE_FLUSH_ALL _IOW(MTK_M4U_MAGICNO, 23, int)
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#define MTK_M4U_T_CONFIG_PORT_ARRAY _IOW(MTK_M4U_MAGICNO, 26, int)
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#define MTK_M4U_T_CONFIG_MAU _IOW(MTK_M4U_MAGICNO, 27, int)
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#define MTK_M4U_T_CONFIG_TF _IOW(MTK_M4U_MAGICNO, 28, int)
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#define MTK_M4U_T_DMA_OP _IOW(MTK_M4U_MAGICNO, 29, int)
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#if IS_ENABLED(CONFIG_COMPAT)
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struct COMPAT_M4U_MOUDLE_STRUCT {
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compat_uint_t port;
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compat_ulong_t BufAddr;
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compat_uint_t BufSize;
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compat_uint_t prot;
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compat_uint_t MVAStart;
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compat_uint_t MVAEnd;
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compat_uint_t flags;
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};
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struct COMPAT_M4U_CACHE_STRUCT {
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compat_uint_t port;
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compat_uint_t eCacheSync;
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compat_ulong_t va;
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compat_uint_t size;
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compat_uint_t mva;
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};
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#define COMPAT_MTK_M4U_T_ALLOC_MVA _IOWR(MTK_M4U_MAGICNO, 4, int)
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#define COMPAT_MTK_M4U_T_DEALLOC_MVA _IOW(MTK_M4U_MAGICNO, 5, int)
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#define COMPAT_MTK_M4U_T_CACHE_SYNC _IOW(MTK_M4U_MAGICNO, 10, int)
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#endif
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#ifdef M4U_TEE_SERVICE_ENABLE
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extern bool m4u_tee_en;
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int smi_reg_restore_sec(void);
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int smi_reg_backup_sec(void);
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/*int m4u_config_port_array_tee(unsigned char* port_array);*/
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int m4u_dump_secpgd(unsigned int larbid, unsigned int portid,
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unsigned long fault_mva);
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#endif
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#endif
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