240 lines
5 KiB
C
240 lines
5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* skl-tplg-interface.h - Intel DSP FW private data interface
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*
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* Copyright (C) 2015 Intel Corp
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* Author: Jeeja KP <jeeja.kp@intel.com>
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* Nilofer, Samreen <samreen.nilofer@intel.com>
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*/
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#ifndef __HDA_TPLG_INTERFACE_H__
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#define __HDA_TPLG_INTERFACE_H__
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#include <linux/types.h>
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/*
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* Default types range from 0~12. type can range from 0 to 0xff
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* SST types start at higher to avoid any overlapping in future
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*/
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#define SKL_CONTROL_TYPE_BYTE_TLV 0x100
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#define SKL_CONTROL_TYPE_MIC_SELECT 0x102
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#define HDA_SST_CFG_MAX 900 /* size of copier cfg*/
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#define MAX_IN_QUEUE 8
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#define MAX_OUT_QUEUE 8
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#define SKL_UUID_STR_SZ 40
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/* Event types goes here */
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/* Reserve event type 0 for no event handlers */
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enum skl_event_types {
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SKL_EVENT_NONE = 0,
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SKL_MIXER_EVENT,
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SKL_MUX_EVENT,
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SKL_VMIXER_EVENT,
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SKL_PGA_EVENT
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};
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/**
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* enum skl_ch_cfg - channel configuration
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*
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* @SKL_CH_CFG_MONO: One channel only
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* @SKL_CH_CFG_STEREO: L & R
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* @SKL_CH_CFG_2_1: L, R & LFE
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* @SKL_CH_CFG_3_0: L, C & R
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* @SKL_CH_CFG_3_1: L, C, R & LFE
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* @SKL_CH_CFG_QUATRO: L, R, Ls & Rs
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* @SKL_CH_CFG_4_0: L, C, R & Cs
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* @SKL_CH_CFG_5_0: L, C, R, Ls & Rs
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* @SKL_CH_CFG_5_1: L, C, R, Ls, Rs & LFE
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* @SKL_CH_CFG_DUAL_MONO: One channel replicated in two
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* @SKL_CH_CFG_I2S_DUAL_STEREO_0: Stereo(L,R) in 4 slots, 1st stream:[ L, R, -, - ]
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* @SKL_CH_CFG_I2S_DUAL_STEREO_1: Stereo(L,R) in 4 slots, 2nd stream:[ -, -, L, R ]
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* @SKL_CH_CFG_INVALID: Invalid
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*/
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enum skl_ch_cfg {
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SKL_CH_CFG_MONO = 0,
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SKL_CH_CFG_STEREO = 1,
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SKL_CH_CFG_2_1 = 2,
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SKL_CH_CFG_3_0 = 3,
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SKL_CH_CFG_3_1 = 4,
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SKL_CH_CFG_QUATRO = 5,
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SKL_CH_CFG_4_0 = 6,
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SKL_CH_CFG_5_0 = 7,
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SKL_CH_CFG_5_1 = 8,
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SKL_CH_CFG_DUAL_MONO = 9,
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SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10,
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SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11,
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SKL_CH_CFG_4_CHANNEL = 12,
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SKL_CH_CFG_INVALID
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};
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enum skl_module_type {
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SKL_MODULE_TYPE_MIXER = 0,
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SKL_MODULE_TYPE_COPIER,
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SKL_MODULE_TYPE_UPDWMIX,
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SKL_MODULE_TYPE_SRCINT,
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SKL_MODULE_TYPE_ALGO,
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SKL_MODULE_TYPE_BASE_OUTFMT,
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SKL_MODULE_TYPE_KPB,
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SKL_MODULE_TYPE_MIC_SELECT,
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};
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enum skl_core_affinity {
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SKL_AFFINITY_CORE_0 = 0,
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SKL_AFFINITY_CORE_1,
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SKL_AFFINITY_CORE_MAX
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};
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enum skl_pipe_conn_type {
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SKL_PIPE_CONN_TYPE_NONE = 0,
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SKL_PIPE_CONN_TYPE_FE,
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SKL_PIPE_CONN_TYPE_BE
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};
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enum skl_hw_conn_type {
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SKL_CONN_NONE = 0,
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SKL_CONN_SOURCE = 1,
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SKL_CONN_SINK = 2
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};
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enum skl_dev_type {
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SKL_DEVICE_BT = 0x0,
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SKL_DEVICE_DMIC = 0x1,
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SKL_DEVICE_I2S = 0x2,
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SKL_DEVICE_SLIMBUS = 0x3,
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SKL_DEVICE_HDALINK = 0x4,
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SKL_DEVICE_HDAHOST = 0x5,
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SKL_DEVICE_NONE
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};
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/**
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* enum skl_interleaving - interleaving style
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*
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* @SKL_INTERLEAVING_PER_CHANNEL: [s1_ch1...s1_chN,...,sM_ch1...sM_chN]
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* @SKL_INTERLEAVING_PER_SAMPLE: [s1_ch1...sM_ch1,...,s1_chN...sM_chN]
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*/
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enum skl_interleaving {
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SKL_INTERLEAVING_PER_CHANNEL = 0,
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SKL_INTERLEAVING_PER_SAMPLE = 1,
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};
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enum skl_sample_type {
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SKL_SAMPLE_TYPE_INT_MSB = 0,
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SKL_SAMPLE_TYPE_INT_LSB = 1,
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SKL_SAMPLE_TYPE_INT_SIGNED = 2,
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SKL_SAMPLE_TYPE_INT_UNSIGNED = 3,
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SKL_SAMPLE_TYPE_FLOAT = 4
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};
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enum module_pin_type {
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/* All pins of the module takes same PCM inputs or outputs
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* e.g. mixout
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*/
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SKL_PIN_TYPE_HOMOGENEOUS,
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/* All pins of the module takes different PCM inputs or outputs
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* e.g mux
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*/
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SKL_PIN_TYPE_HETEROGENEOUS,
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};
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enum skl_module_param_type {
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SKL_PARAM_DEFAULT = 0,
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SKL_PARAM_INIT,
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SKL_PARAM_SET,
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SKL_PARAM_BIND
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};
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struct skl_dfw_algo_data {
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__u32 set_params:2;
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__u32 rsvd:30;
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__u32 param_id;
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__u32 max;
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char params[0];
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} __packed;
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enum skl_tkn_dir {
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SKL_DIR_IN,
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SKL_DIR_OUT
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};
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enum skl_tuple_type {
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SKL_TYPE_TUPLE,
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SKL_TYPE_DATA
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};
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/* v4 configuration data */
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struct skl_dfw_v4_module_pin {
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__u16 module_id;
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__u16 instance_id;
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} __packed;
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struct skl_dfw_v4_module_fmt {
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__u32 channels;
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__u32 freq;
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__u32 bit_depth;
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__u32 valid_bit_depth;
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__u32 ch_cfg;
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__u32 interleaving_style;
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__u32 sample_type;
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__u32 ch_map;
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} __packed;
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struct skl_dfw_v4_module_caps {
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__u32 set_params:2;
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__u32 rsvd:30;
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__u32 param_id;
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__u32 caps_size;
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__u32 caps[HDA_SST_CFG_MAX];
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} __packed;
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struct skl_dfw_v4_pipe {
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__u8 pipe_id;
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__u8 pipe_priority;
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__u16 conn_type:4;
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__u16 rsvd:4;
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__u16 memory_pages:8;
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} __packed;
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struct skl_dfw_v4_module {
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char uuid[SKL_UUID_STR_SZ];
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__u16 module_id;
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__u16 instance_id;
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__u32 max_mcps;
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__u32 mem_pages;
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__u32 obs;
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__u32 ibs;
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__u32 vbus_id;
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__u32 max_in_queue:8;
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__u32 max_out_queue:8;
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__u32 time_slot:8;
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__u32 core_id:4;
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__u32 rsvd1:4;
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__u32 module_type:8;
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__u32 conn_type:4;
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__u32 dev_type:4;
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__u32 hw_conn_type:4;
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__u32 rsvd2:12;
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__u32 params_fixup:8;
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__u32 converter:8;
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__u32 input_pin_type:1;
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__u32 output_pin_type:1;
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__u32 is_dynamic_in_pin:1;
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__u32 is_dynamic_out_pin:1;
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__u32 is_loadable:1;
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__u32 rsvd3:11;
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struct skl_dfw_v4_pipe pipe;
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struct skl_dfw_v4_module_fmt in_fmt[MAX_IN_QUEUE];
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struct skl_dfw_v4_module_fmt out_fmt[MAX_OUT_QUEUE];
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struct skl_dfw_v4_module_pin in_pin[MAX_IN_QUEUE];
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struct skl_dfw_v4_module_pin out_pin[MAX_OUT_QUEUE];
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struct skl_dfw_v4_module_caps caps;
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} __packed;
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#endif
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