528 lines
15 KiB
C
528 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* cs35l43-tables.c -- CS35L43 ALSA SoC audio driver
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*
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* Copyright 2021 Cirrus Logic, Inc.
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*
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* Author: David Rhodes <david.rhodes@cirrus.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include "wm_adsp.h"
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#include "cs35l43.h"
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#include <sound/cs35l43.h>
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bool cs35l43_readable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case CS35L43_DEVID:
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case CS35L43_REVID:
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case CS35L43_FABID:
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case CS35L43_RELID:
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case CS35L43_OTPID:
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case CS35L43_SFT_RESET:
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case CS35L43_TEST_KEY_CTRL:
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case CS35L43_USER_KEY_CTRL:
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case CS35L43_CTRL_ASYNC0:
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case CS35L43_CTRL_ASYNC1:
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case CS35L43_CTRL_ASYNC2:
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case CS35L43_CTRL_ASYNC3:
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case CS35L43_CTRL_IF_CONFIG1:
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case CS35L43_CTRL_IF_STATUS1:
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case CS35L43_CTRL_IF_STATUS2:
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case CS35L43_CTRL_IF_CONFIG2:
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case CS35L43_CTRL_IF_DEBUG1:
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case CS35L43_CTRL_IF_DEBUG2:
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case CS35L43_CTRL_IF_DEBUG3:
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case CS35L43_CIF_MON1:
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case CS35L43_CIF_MON2:
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case CS35L43_CIF_MON_PADDR:
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case CS35L43_CTRL_IF_SPARE1:
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case CS35L43_CTRL_IF_I2C:
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case CS35L43_CTRL_IF_I2C_1_CONTROL:
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case CS35L43_CTRL_IF_I2C_1_BROADCAST:
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case CS35L43_APB_MSTR_DSP_BRIDGE_ERR:
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case CS35L43_CIF1_BRIDGE_ERR:
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case CS35L43_CIF2_BRIDGE_ERR:
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case CS35L43_OTP_MEM0 ... CS35L43_OTP_MEM31:
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case CS35L43_OTP_CTRL0:
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case CS35L43_OTP_CTRL1:
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case CS35L43_OTP_CTRL3:
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case CS35L43_OTP_CTRL4:
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case CS35L43_OTP_CTRL5:
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case CS35L43_OTP_CTRL6:
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case CS35L43_OTP_CTRL7:
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case CS35L43_OTP_CTRL8:
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case CS35L43_DEVICE_ID:
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case CS35L43_FAB_ID:
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case CS35L43_REV_ID:
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case CS35L43_GLOBAL_ENABLES:
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case CS35L43_BLOCK_ENABLES:
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case CS35L43_BLOCK_ENABLES2:
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case CS35L43_GLOBAL_OVERRIDES:
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case CS35L43_GLOBAL_SYNC:
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case CS35L43_GLOBAL_STATUS:
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case CS35L43_DISCH_FILT:
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case CS35L43_OSC_TRIM:
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case CS35L43_ERROR_RELEASE:
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case CS35L43_PLL_OVERRIDE:
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case CS35L43_CHIP_STATUS:
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case CS35L43_CHIP_STATUS2:
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case CS35L43_LRCK_PAD_CONTROL:
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case CS35L43_SCLK_PAD_CONTROL:
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case CS35L43_SDIN_PAD_CONTROL:
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case CS35L43_SDOUT_PAD_CONTROL:
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case CS35L43_GPIO_PAD_CONTROL:
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case CS35L43_GPIO_GLOBAL_ENABLE_CONTROL:
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case CS35L43_PWRMGT_CTL:
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case CS35L43_WAKESRC_CTL:
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case CS35L43_WAKEI2C_CTL:
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case CS35L43_PWRMGT_STS:
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case CS35L43_PWRMGT_RST:
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case CS35L43_TEST_CTL:
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case CS35L43_REFCLK_INPUT:
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case CS35L43_DSP_CLOCK_GEARING:
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case CS35L43_GLOBAL_SAMPLE_RATE:
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case CS35L43_DSP1_SAMPLE_RATE_RX1:
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case CS35L43_DSP1_SAMPLE_RATE_RX2:
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case CS35L43_DSP1_SAMPLE_RATE_TX1:
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case CS35L43_DSP1_SAMPLE_RATE_TX2:
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case CS35L43_SYNC_TX_RX_ENABLES:
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case CS35L43_VBST_CTL_1:
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case CS35L43_VBST_CTL_2:
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case CS35L43_BST_IPK_CTL:
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case CS35L43_SOFT_RAMP:
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case CS35L43_BST_LOOP_COEFF:
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case CS35L43_LBST_SLOPE:
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case CS35L43_BST_SW_FREQ:
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case CS35L43_BST_DCM_CTL:
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case CS35L43_DCM_FORCE:
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case CS35L43_VBST_OVP:
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case CS35L43_MONITOR_FILT:
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case CS35L43_WARN_LIMIT_THRESHOLD:
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case CS35L43_CONFIGURATION:
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case CS35L43_STATUS:
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case CS35L43_ENABLES_AND_CODES_ANA:
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case CS35L43_ENABLES_AND_CODES_DIG:
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case CS35L43_ASP_ENABLES1:
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case CS35L43_ASP_CONTROL1:
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case CS35L43_ASP_CONTROL2:
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case CS35L43_ASP_CONTROL3:
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case CS35L43_ASP_FRAME_CONTROL1:
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case CS35L43_ASP_FRAME_CONTROL5:
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case CS35L43_ASP_DATA_CONTROL1:
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case CS35L43_ASP_DATA_CONTROL5:
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case CS35L43_DACPCM1_INPUT:
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case CS35L43_DACPCM2_INPUT:
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case CS35L43_ASPTX1_INPUT:
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case CS35L43_ASPTX2_INPUT:
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case CS35L43_ASPTX3_INPUT:
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case CS35L43_ASPTX4_INPUT:
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case CS35L43_DSP1RX1_INPUT:
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case CS35L43_DSP1RX2_INPUT:
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case CS35L43_DSP1RX3_INPUT:
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case CS35L43_DSP1RX4_INPUT:
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case CS35L43_DSP1RX5_INPUT:
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case CS35L43_DSP1RX6_INPUT:
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case CS35L43_NGATE1_INPUT:
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case CS35L43_NGATE2_INPUT:
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case CS35L43_AMP_CTRL:
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case CS35L43_HPF_TST:
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case CS35L43_VC_TST1:
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case CS35L43_VC_TST2:
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case CS35L43_INTP_TST:
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case CS35L43_SRC_MAGCOMP_TST:
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case CS35L43_SRC_MAGCOMP_B0_OVERRIDE:
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case CS35L43_SRC_MAGCOMP_B1_OVERRIDE:
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case CS35L43_SRC_MAGCOMP_A1_N_OVERRIDE:
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case CS35L43_VPBR_CONFIG:
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case CS35L43_VBBR_CONFIG:
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case CS35L43_VPBR_STATUS:
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case CS35L43_VBBR_STATUS:
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case CS35L43_OTW_CONFIG:
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case CS35L43_AMP_ERROR_VOL_SEL:
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case CS35L43_VOL_STATUS_TO_DSP:
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case CS35L43_CLASSH_CONFIG:
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case CS35L43_WKFET_AMP_CONFIG:
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case CS35L43_NG_CONFIG:
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case CS35L43_AMP_GAIN:
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case CS35L43_DAC_MSM_CONFIG:
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case CS35L43_TST_DAC_MSM_CONFIG:
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case CS35L43_ALIVE_DCIN_WD:
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case CS35L43_IRQ1_CFG:
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case CS35L43_IRQ1_STATUS:
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case CS35L43_IRQ1_EINT_1:
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case CS35L43_IRQ1_EINT_2:
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case CS35L43_IRQ1_EINT_3:
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case CS35L43_IRQ1_EINT_4:
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case CS35L43_IRQ1_EINT_5:
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case CS35L43_IRQ1_STS_1:
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case CS35L43_IRQ1_STS_2:
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case CS35L43_IRQ1_STS_3:
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case CS35L43_IRQ1_STS_4:
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case CS35L43_IRQ1_STS_5:
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case CS35L43_IRQ1_MASK_1:
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case CS35L43_IRQ1_MASK_2:
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case CS35L43_IRQ1_MASK_3:
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case CS35L43_IRQ1_MASK_4:
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case CS35L43_IRQ1_MASK_5:
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case CS35L43_IRQ1_FRC_1:
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case CS35L43_IRQ1_FRC_2:
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case CS35L43_IRQ1_FRC_3:
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case CS35L43_IRQ1_FRC_4:
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case CS35L43_IRQ1_FRC_5:
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case CS35L43_IRQ1_EDGE_1:
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case CS35L43_IRQ1_EDGE_4:
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case CS35L43_IRQ1_POL_1:
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case CS35L43_IRQ1_POL_2:
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case CS35L43_IRQ1_POL_3:
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case CS35L43_IRQ1_POL_4:
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case CS35L43_IRQ1_DB_2:
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case CS35L43_GPIO_STATUS1:
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case CS35L43_GPIO_FORCE:
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case CS35L43_GPIO1_CTRL1:
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case CS35L43_GPIO2_CTRL1:
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case CS35L43_GPIO3_CTRL1:
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case CS35L43_GPIO4_CTRL1:
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case CS35L43_MIXER_NGATE_CFG:
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case CS35L43_MIXER_NGATE_CH1_CFG:
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case CS35L43_MIXER_NGATE_CH2_CFG:
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case CS35L43_DSP_MBOX_1:
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case CS35L43_DSP_MBOX_2:
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case CS35L43_DSP_MBOX_3:
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case CS35L43_DSP_MBOX_4:
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case CS35L43_DSP_MBOX_5:
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case CS35L43_DSP_MBOX_6:
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case CS35L43_DSP_MBOX_7:
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case CS35L43_DSP_MBOX_8:
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case CS35L43_DSP_VIRTUAL1_MBOX_1:
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case CS35L43_DSP_VIRTUAL1_MBOX_2:
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case CS35L43_DSP_VIRTUAL1_MBOX_3:
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case CS35L43_DSP_VIRTUAL1_MBOX_4:
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case CS35L43_DSP_VIRTUAL1_MBOX_5:
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case CS35L43_DSP_VIRTUAL1_MBOX_6:
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case CS35L43_DSP_VIRTUAL1_MBOX_7:
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case CS35L43_DSP_VIRTUAL1_MBOX_8:
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case CS35L43_DSP_VIRTUAL2_MBOX_1:
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case CS35L43_DSP_VIRTUAL2_MBOX_2:
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case CS35L43_DSP_VIRTUAL2_MBOX_3:
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case CS35L43_DSP_VIRTUAL2_MBOX_4:
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case CS35L43_DSP_VIRTUAL2_MBOX_5:
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case CS35L43_DSP_VIRTUAL2_MBOX_6:
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case CS35L43_DSP_VIRTUAL2_MBOX_7:
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case CS35L43_DSP_VIRTUAL2_MBOX_8:
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case CS35L43_DSP1_SYS_INFO_ID:
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case CS35L43_DSP1_CLOCK_FREQ:
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case CS35L43_DSP1_SCRATCH1:
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case CS35L43_DSP1_SCRATCH2:
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case CS35L43_DSP1_SCRATCH3:
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case CS35L43_DSP1_SCRATCH4:
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case CS35L43_DSP1_CCM_CORE_CONTROL:
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case CS35L43_DSP1_XMEM_PACKED_0 ... CS35L43_DSP1_XMEM_PACKED_6143:
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case CS35L43_DSP1_XMEM_UNPACKED32_0 ...
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CS35L43_DSP1_XMEM_UNPACKED32_4095:
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case CS35L43_DSP1_XMEM_UNPACKED24_0 ...
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CS35L43_DSP1_XMEM_UNPACKED24_8191:
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case CS35L43_DSP1_XROM_UNPACKED24_0 ...
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CS35L43_DSP1_XROM_UNPACKED24_6141:
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case CS35L43_DSP1_YMEM_PACKED_0 ... CS35L43_DSP1_YMEM_PACKED_1532:
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case CS35L43_DSP1_YMEM_UNPACKED32_0 ...
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CS35L43_DSP1_YMEM_UNPACKED32_1022:
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case CS35L43_DSP1_YMEM_UNPACKED24_0 ...
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CS35L43_DSP1_YMEM_UNPACKED24_2045:
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case CS35L43_DSP1_PMEM_0 ... CS35L43_DSP1_PMEM_5114:
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return true;
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default:
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return false;
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}
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}
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bool cs35l43_precious_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case CS35L43_DSP1_XMEM_PACKED_0 ... CS35L43_DSP1_XMEM_PACKED_6143:
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case CS35L43_DSP1_XMEM_UNPACKED32_0 ...
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CS35L43_DSP1_XMEM_UNPACKED32_4095:
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case CS35L43_DSP1_XROM_UNPACKED24_0 ...
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CS35L43_DSP1_XROM_UNPACKED24_6141:
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case CS35L43_DSP1_YMEM_PACKED_0 ... CS35L43_DSP1_YMEM_PACKED_1532:
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case CS35L43_DSP1_YMEM_UNPACKED32_0 ...
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CS35L43_DSP1_YMEM_UNPACKED32_1022:
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case CS35L43_DSP1_PMEM_0 ... CS35L43_DSP1_PMEM_5114:
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return true;
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default:
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return false;
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}
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return false;
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}
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bool cs35l43_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case CS35L43_GLOBAL_STATUS:
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case CS35L43_CHIP_STATUS:
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case CS35L43_CHIP_STATUS2:
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case CS35L43_STATUS:
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case CS35L43_ENABLES_AND_CODES_ANA:
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case CS35L43_ENABLES_AND_CODES_DIG:
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case CS35L43_VPBR_STATUS:
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case CS35L43_VBBR_STATUS:
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case CS35L43_IRQ1_STATUS:
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case CS35L43_IRQ1_EINT_1:
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case CS35L43_IRQ1_EINT_2:
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case CS35L43_IRQ1_EINT_3:
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case CS35L43_IRQ1_EINT_4:
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case CS35L43_IRQ1_EINT_5:
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case CS35L43_IRQ1_STS_1:
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case CS35L43_IRQ1_STS_2:
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case CS35L43_IRQ1_STS_3:
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case CS35L43_IRQ1_STS_4:
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case CS35L43_IRQ1_STS_5:
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case CS35L43_GPIO_STATUS1:
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case CS35L43_DSP_MBOX_1:
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case CS35L43_DSP_MBOX_2:
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case CS35L43_DSP_MBOX_3:
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case CS35L43_DSP_MBOX_4:
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case CS35L43_DSP_MBOX_5:
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case CS35L43_DSP_MBOX_6:
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case CS35L43_DSP_MBOX_7:
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case CS35L43_DSP_MBOX_8:
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case CS35L43_DSP_VIRTUAL1_MBOX_1:
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case CS35L43_DSP_VIRTUAL1_MBOX_2:
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case CS35L43_DSP_VIRTUAL1_MBOX_3:
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case CS35L43_DSP_VIRTUAL1_MBOX_4:
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case CS35L43_DSP_VIRTUAL1_MBOX_5:
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case CS35L43_DSP_VIRTUAL1_MBOX_6:
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case CS35L43_DSP_VIRTUAL1_MBOX_7:
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case CS35L43_DSP_VIRTUAL1_MBOX_8:
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case CS35L43_DSP_VIRTUAL2_MBOX_1:
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case CS35L43_DSP_VIRTUAL2_MBOX_2:
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case CS35L43_DSP_VIRTUAL2_MBOX_3:
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case CS35L43_DSP_VIRTUAL2_MBOX_4:
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case CS35L43_DSP_VIRTUAL2_MBOX_5:
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case CS35L43_DSP_VIRTUAL2_MBOX_6:
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case CS35L43_DSP_VIRTUAL2_MBOX_7:
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case CS35L43_DSP_VIRTUAL2_MBOX_8:
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case CS35L43_DSP1_SCRATCH1:
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case CS35L43_DSP1_SCRATCH2:
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case CS35L43_DSP1_SCRATCH3:
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case CS35L43_DSP1_SCRATCH4:
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case CS35L43_DSP1_XMEM_PACKED_0 ...
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CS35L43_DSP1_XMEM_PACKED_6143:
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case CS35L43_DSP1_XMEM_UNPACKED32_0 ...
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CS35L43_DSP1_XMEM_UNPACKED32_4095:
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case CS35L43_DSP1_XMEM_UNPACKED24_0 ...
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CS35L43_DSP1_XMEM_UNPACKED24_8191:
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case CS35L43_DSP1_XROM_UNPACKED24_0 ...
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CS35L43_DSP1_XROM_UNPACKED24_6141:
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case CS35L43_DSP1_YMEM_PACKED_0 ...
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CS35L43_DSP1_YMEM_PACKED_1532:
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case CS35L43_DSP1_YMEM_UNPACKED32_0 ...
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CS35L43_DSP1_YMEM_UNPACKED32_1022:
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case CS35L43_DSP1_YMEM_UNPACKED24_0 ...
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CS35L43_DSP1_YMEM_UNPACKED24_2045:
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case CS35L43_DSP1_PMEM_0 ...
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CS35L43_DSP1_PMEM_5114:
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return true;
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default:
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return false;
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}
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}
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const struct reg_default cs35l43_reg[CS35L43_NUM_DEFAULTS] = {
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{ CS35L43_CTRL_ASYNC0, 0x00000000 },
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{ CS35L43_CTRL_ASYNC1, 0x00000004 },
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{ CS35L43_CTRL_ASYNC2, 0x00000000 },
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{ CS35L43_CTRL_ASYNC3, 0x00000000 },
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{ CS35L43_CTRL_IF_CONFIG1, 0x00020002 },
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{ CS35L43_CTRL_IF_STATUS1, 0x00000000 },
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{ CS35L43_CTRL_IF_STATUS2, 0x00000000 },
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{ CS35L43_CTRL_IF_CONFIG2, 0x00000000 },
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{ CS35L43_CTRL_IF_DEBUG1, 0x00000000 },
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{ CS35L43_CTRL_IF_DEBUG2, 0x00000000 },
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{ CS35L43_CTRL_IF_DEBUG3, 0x00000000 },
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{ CS35L43_CIF_MON1, 0x00002003 },
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{ CS35L43_CIF_MON2, 0x00000000 },
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{ CS35L43_CIF_MON_PADDR, 0x00000000 },
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{ CS35L43_CTRL_IF_SPARE1, 0x00000000 },
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{ CS35L43_CTRL_IF_I2C, 0x00000004 },
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{ CS35L43_CTRL_IF_I2C_1_CONTROL, 0x00000040 },
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{ CS35L43_CTRL_IF_I2C_1_BROADCAST, 0x00000088 },
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{ CS35L43_APB_MSTR_DSP_BRIDGE_ERR, 0x00000000 },
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{ CS35L43_CIF1_BRIDGE_ERR, 0x00000000 },
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{ CS35L43_CIF2_BRIDGE_ERR, 0x00000000 },
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{ CS35L43_LRCK_PAD_CONTROL, 0x00000007 },
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{ CS35L43_SCLK_PAD_CONTROL, 0x00000007 },
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{ CS35L43_SDIN_PAD_CONTROL, 0x00000007 },
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{ CS35L43_HPF_TST, 0x00000000 },
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{ CS35L43_VC_TST1, 0x00000000 },
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{ CS35L43_VC_TST2, 0x00000000 },
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{ CS35L43_INTP_TST, 0x00000680 },
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{ CS35L43_SRC_MAGCOMP_TST, 0x0000000D },
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{ CS35L43_SRC_MAGCOMP_B0_OVERRIDE, 0x00000000 },
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{ CS35L43_SRC_MAGCOMP_B1_OVERRIDE, 0x00000000 },
|
|
{ CS35L43_SRC_MAGCOMP_A1_N_OVERRIDE, 0x00000000 },
|
|
{ CS35L43_OTW_CONFIG, 0x00000001 },
|
|
{ CS35L43_AMP_ERROR_VOL_SEL, 0x00000000 },
|
|
{ CS35L43_VOL_STATUS_TO_DSP, 0x00000000 },
|
|
{ CS35L43_IRQ1_POL_1, 0x00000000 },
|
|
{ CS35L43_IRQ1_POL_2, 0x00000000 },
|
|
{ CS35L43_IRQ1_POL_3, 0x00000000 },
|
|
{ CS35L43_IRQ1_POL_4, 0x00000000 },
|
|
{ CS35L43_GPIO3_CTRL1, 0x80000001 },
|
|
{ CS35L43_GPIO4_CTRL1, 0x80000001 },
|
|
};
|
|
|
|
const unsigned int cs35l43_hibernate_update_regs[CS35L43_POWER_SEQ_LENGTH] = {
|
|
CS35L43_ASPTX1_INPUT,
|
|
CS35L43_ASPTX2_INPUT,
|
|
CS35L43_ASPTX3_INPUT,
|
|
CS35L43_ASPTX4_INPUT,
|
|
CS35L43_DSP1RX1_INPUT,
|
|
CS35L43_DSP1RX2_INPUT,
|
|
CS35L43_DSP1RX3_INPUT,
|
|
CS35L43_DSP1RX4_INPUT,
|
|
CS35L43_DSP1RX5_INPUT,
|
|
CS35L43_DSP1RX6_INPUT,
|
|
CS35L43_DACPCM1_INPUT,
|
|
CS35L43_DACPCM2_INPUT,
|
|
CS35L43_ASP_FRAME_CONTROL1,
|
|
CS35L43_ASP_FRAME_CONTROL5,
|
|
CS35L43_AMP_CTRL,
|
|
CS35L43_AMP_GAIN,
|
|
CS35L43_GLOBAL_SAMPLE_RATE,
|
|
CS35L43_DSP1_SAMPLE_RATE_RX1,
|
|
CS35L43_DSP1_SAMPLE_RATE_RX2,
|
|
CS35L43_DSP1_SAMPLE_RATE_TX1,
|
|
CS35L43_DSP1_SAMPLE_RATE_TX2,
|
|
CS35L43_ALIVE_DCIN_WD,
|
|
CS35L43_MONITOR_FILT,
|
|
CS35L43_DAC_MSM_CONFIG,
|
|
CS35L43_ASP_CONTROL2,
|
|
CS35L43_ASP_CONTROL3,
|
|
CS35L43_ASP_DATA_CONTROL1,
|
|
CS35L43_ASP_DATA_CONTROL5,
|
|
CS35L43_GPIO_PAD_CONTROL,
|
|
CS35L43_VBST_CTL_1,
|
|
CS35L43_VBST_CTL_2,
|
|
CS35L43_BST_IPK_CTL,
|
|
CS35L43_VPBR_CONFIG,
|
|
CS35L43_GLOBAL_SYNC,
|
|
CS35L43_BLOCK_ENABLES,
|
|
CS35L43_BLOCK_ENABLES2,
|
|
CS35L43_NG_CONFIG,
|
|
CS35L43_MIXER_NGATE_CH1_CFG,
|
|
CS35L43_MIXER_NGATE_CH2_CFG,
|
|
CS35L43_FS_MON_0,
|
|
CS35L43_TST_DAC_MSM_CONFIG,
|
|
};
|
|
|
|
const struct cs35l43_pll_sysclk_config cs35l43_pll_sysclk[64] = {
|
|
{ 32768, 0x00 },
|
|
{ 8000, 0x01 },
|
|
{ 11025, 0x02 },
|
|
{ 12000, 0x03 },
|
|
{ 16000, 0x04 },
|
|
{ 22050, 0x05 },
|
|
{ 24000, 0x06 },
|
|
{ 32000, 0x07 },
|
|
{ 44100, 0x08 },
|
|
{ 48000, 0x09 },
|
|
{ 88200, 0x0A },
|
|
{ 96000, 0x0B },
|
|
{ 128000, 0x0C },
|
|
{ 176400, 0x0D },
|
|
{ 192000, 0x0E },
|
|
{ 256000, 0x0F },
|
|
{ 352800, 0x10 },
|
|
{ 384000, 0x11 },
|
|
{ 512000, 0x12 },
|
|
{ 705600, 0x13 },
|
|
{ 750000, 0x14 },
|
|
{ 768000, 0x15 },
|
|
{ 1000000, 0x16 },
|
|
{ 1024000, 0x17 },
|
|
{ 1200000, 0x18 },
|
|
{ 1411200, 0x19 },
|
|
{ 1500000, 0x1A },
|
|
{ 1536000, 0x1B },
|
|
{ 2000000, 0x1C },
|
|
{ 2048000, 0x1D },
|
|
{ 2400000, 0x1E },
|
|
{ 2822400, 0x1F },
|
|
{ 3000000, 0x20 },
|
|
{ 3072000, 0x21 },
|
|
{ 3200000, 0x22 },
|
|
{ 4000000, 0x23 },
|
|
{ 4096000, 0x24 },
|
|
{ 4800000, 0x25 },
|
|
{ 5644800, 0x26 },
|
|
{ 6000000, 0x27 },
|
|
{ 6144000, 0x28 },
|
|
{ 6250000, 0x29 },
|
|
{ 6400000, 0x2A },
|
|
{ 6500000, 0x2B },
|
|
{ 6750000, 0x2C },
|
|
{ 7526400, 0x2D },
|
|
{ 8000000, 0x2E },
|
|
{ 8192000, 0x2F },
|
|
{ 9600000, 0x30 },
|
|
{ 11289600, 0x31 },
|
|
{ 12000000, 0x32 },
|
|
{ 12288000, 0x33 },
|
|
{ 12500000, 0x34 },
|
|
{ 12800000, 0x35 },
|
|
{ 13000000, 0x36 },
|
|
{ 13500000, 0x37 },
|
|
{ 19200000, 0x38 },
|
|
{ 22579200, 0x39 },
|
|
{ 24000000, 0x3A },
|
|
{ 24576000, 0x3B },
|
|
{ 25000000, 0x3C },
|
|
{ 25600000, 0x3D },
|
|
{ 26000000, 0x3E },
|
|
{ 27000000, 0x3F },
|
|
};
|
|
|
|
const struct cs35l43_fs_mon_config cs35l43_fs_mon[7] = {
|
|
{ 705600, 154, 244 },
|
|
{ 768000, 141, 224 },
|
|
{ 1411200, 77, 125 },
|
|
{ 1536000, 71, 115 },
|
|
{ 2822400, 39, 65 },
|
|
{ 3072000, 36, 60 },
|
|
{ 5644800, 20, 35 },
|
|
};
|
|
|
|
const u8 cs35l43_write_seq_op_sizes[CS35L43_POWER_SEQ_NUM_OPS][2] = {
|
|
{ CS35L43_POWER_SEQ_OP_WRITE_REG_FULL,
|
|
CS35L43_POWER_SEQ_OP_WRITE_REG_FULL_WORDS},
|
|
{ CS35L43_POWER_SEQ_OP_WRITE_FIELD,
|
|
CS35L43_POWER_SEQ_OP_WRITE_FIELD_WORDS},
|
|
{ CS35L43_POWER_SEQ_OP_WRITE_REG_ADDR8,
|
|
CS35L43_POWER_SEQ_OP_WRITE_REG_ADDR8_WORDS},
|
|
{ CS35L43_POWER_SEQ_OP_WRITE_REG_INCR,
|
|
CS35L43_POWER_SEQ_OP_WRITE_REG_INCR_WORDS},
|
|
{ CS35L43_POWER_SEQ_OP_WRITE_REG_L16,
|
|
CS35L43_POWER_SEQ_OP_WRITE_REG_L16_WORDS},
|
|
{ CS35L43_POWER_SEQ_OP_WRITE_REG_H16,
|
|
CS35L43_POWER_SEQ_OP_WRITE_REG_H16_WORDS},
|
|
{ CS35L43_POWER_SEQ_OP_DELAY,
|
|
CS35L43_POWER_SEQ_OP_DELAY_WORDS},
|
|
{ CS35L43_POWER_SEQ_OP_END,
|
|
CS35L43_POWER_SEQ_OP_END_WORDS},
|
|
};
|
|
|
|
const struct dev_pm_ops cs35l43_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(cs35l43_suspend_runtime, cs35l43_resume_runtime, NULL)
|
|
};
|