829 lines
36 KiB
C
829 lines
36 KiB
C
/*
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* Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef _TFA9874_TFAFIELDNAMES_H
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#define _TFA9874_TFAFIELDNAMES_H
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#define TFA9874_I2CVERSION 1.16
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enum nxpTfa9874BfEnumList {
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TFA9874_BF_PWDN = 0x0000,
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TFA9874_BF_I2CR = 0x0010,
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TFA9874_BF_AMPE = 0x0030,
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TFA9874_BF_DCA = 0x0040,
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TFA9874_BF_INTP = 0x0071,
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TFA9874_BF_BYPOCP = 0x00b0,
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TFA9874_BF_TSTOCP = 0x00c0,
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TFA9874_BF_MANSCONF = 0x0120,
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TFA9874_BF_MANAOOSC = 0x0140,
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TFA9874_BF_MUTETO = 0x01d0,
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TFA9874_BF_OPENMTP = 0x01e0,
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TFA9874_BF_AUDFS = 0x0203,
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TFA9874_BF_INPLEV = 0x0240,
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TFA9874_BF_FRACTDEL = 0x0255,
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TFA9874_BF_REV = 0x030f,
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TFA9874_BF_REFCKEXT = 0x0401,
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TFA9874_BF_REFCKSEL = 0x0420,
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TFA9874_BF_SSFAIME = 0x05c0,
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TFA9874_BF_AMPOCRT = 0x0802,
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TFA9874_BF_VDDS = 0x1000,
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TFA9874_BF_DCOCPOK = 0x1010,
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TFA9874_BF_OTDS = 0x1020,
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TFA9874_BF_OCDS = 0x1030,
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TFA9874_BF_UVDS = 0x1040,
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TFA9874_BF_MANALARM = 0x1050,
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TFA9874_BF_TDMERR = 0x1060,
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TFA9874_BF_NOCLK = 0x1070,
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TFA9874_BF_DCIL = 0x1100,
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TFA9874_BF_DCDCA = 0x1110,
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TFA9874_BF_DCHVBAT = 0x1130,
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TFA9874_BF_DCH114 = 0x1140,
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TFA9874_BF_DCH107 = 0x1150,
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TFA9874_BF_PLLS = 0x1160,
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TFA9874_BF_CLKS = 0x1170,
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TFA9874_BF_TDMLUTER = 0x1180,
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TFA9874_BF_TDMSTAT = 0x1192,
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TFA9874_BF_MTPB = 0x11c0,
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TFA9874_BF_SWS = 0x11d0,
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TFA9874_BF_AMPS = 0x11e0,
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TFA9874_BF_AREFS = 0x11f0,
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TFA9874_BF_OCPOAP = 0x1300,
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TFA9874_BF_OCPOAN = 0x1310,
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TFA9874_BF_OCPOBP = 0x1320,
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TFA9874_BF_OCPOBN = 0x1330,
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TFA9874_BF_OVDS = 0x1380,
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TFA9874_BF_CLIPS = 0x1390,
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TFA9874_BF_ADCCR = 0x13a0,
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TFA9874_BF_MANWAIT1 = 0x13c0,
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TFA9874_BF_MANMUTE = 0x13e0,
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TFA9874_BF_MANOPER = 0x13f0,
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TFA9874_BF_CLKOOR = 0x1420,
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TFA9874_BF_MANSTATE = 0x1433,
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TFA9874_BF_DCMODE = 0x1471,
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TFA9874_BF_BATS = 0x1509,
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TFA9874_BF_TEMPS = 0x1608,
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TFA9874_BF_VDDPS = 0x1709,
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TFA9874_BF_TDME = 0x2040,
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TFA9874_BF_TDMMODE = 0x2050,
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TFA9874_BF_TDMCLINV = 0x2060,
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TFA9874_BF_TDMFSLN = 0x2073,
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TFA9874_BF_TDMFSPOL = 0x20b0,
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TFA9874_BF_TDMNBCK = 0x20c3,
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TFA9874_BF_TDMSLOTS = 0x2103,
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TFA9874_BF_TDMSLLN = 0x2144,
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TFA9874_BF_TDMBRMG = 0x2194,
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TFA9874_BF_TDMDEL = 0x21e0,
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TFA9874_BF_TDMADJ = 0x21f0,
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TFA9874_BF_TDMOOMP = 0x2201,
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TFA9874_BF_TDMSSIZE = 0x2224,
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TFA9874_BF_TDMTXDFO = 0x2271,
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TFA9874_BF_TDMTXUS0 = 0x2291,
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TFA9874_BF_TDMSPKE = 0x2300,
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TFA9874_BF_TDMDCE = 0x2310,
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TFA9874_BF_TDMCSE = 0x2330,
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TFA9874_BF_TDMVSE = 0x2340,
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TFA9874_BF_TDMSPKS = 0x2603,
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TFA9874_BF_TDMDCS = 0x2643,
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TFA9874_BF_TDMCSS = 0x26c3,
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TFA9874_BF_TDMVSS = 0x2703,
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TFA9874_BF_ISTVDDS = 0x4000,
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TFA9874_BF_ISTBSTOC = 0x4010,
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TFA9874_BF_ISTOTDS = 0x4020,
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TFA9874_BF_ISTOCPR = 0x4030,
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TFA9874_BF_ISTUVDS = 0x4040,
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TFA9874_BF_ISTMANALARM = 0x4050,
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TFA9874_BF_ISTTDMER = 0x4060,
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TFA9874_BF_ISTNOCLK = 0x4070,
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TFA9874_BF_ICLVDDS = 0x4400,
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TFA9874_BF_ICLBSTOC = 0x4410,
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TFA9874_BF_ICLOTDS = 0x4420,
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TFA9874_BF_ICLOCPR = 0x4430,
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TFA9874_BF_ICLUVDS = 0x4440,
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TFA9874_BF_ICLMANALARM = 0x4450,
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TFA9874_BF_ICLTDMER = 0x4460,
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TFA9874_BF_ICLNOCLK = 0x4470,
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TFA9874_BF_IEVDDS = 0x4800,
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TFA9874_BF_IEBSTOC = 0x4810,
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TFA9874_BF_IEOTDS = 0x4820,
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TFA9874_BF_IEOCPR = 0x4830,
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TFA9874_BF_IEUVDS = 0x4840,
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TFA9874_BF_IEMANALARM = 0x4850,
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TFA9874_BF_IETDMER = 0x4860,
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TFA9874_BF_IENOCLK = 0x4870,
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TFA9874_BF_IPOVDDS = 0x4c00,
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TFA9874_BF_IPOBSTOC = 0x4c10,
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TFA9874_BF_IPOOTDS = 0x4c20,
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TFA9874_BF_IPOOCPR = 0x4c30,
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TFA9874_BF_IPOUVDS = 0x4c40,
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TFA9874_BF_IPOMANALARM = 0x4c50,
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TFA9874_BF_IPOTDMER = 0x4c60,
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TFA9874_BF_IPONOCLK = 0x4c70,
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TFA9874_BF_BSSCR = 0x5001,
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TFA9874_BF_BSST = 0x5023,
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TFA9874_BF_BSSRL = 0x5061,
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TFA9874_BF_VBATFLTL = 0x5080,
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TFA9874_BF_BSSR = 0x50e0,
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TFA9874_BF_BSSBY = 0x50f0,
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TFA9874_BF_BSSS = 0x5100,
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TFA9874_BF_HPFBYP = 0x5150,
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TFA9874_BF_DPSA = 0x5170,
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TFA9874_BF_CLIPCTRL = 0x5222,
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TFA9874_BF_AMPGAIN = 0x5257,
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TFA9874_BF_SLOPEE = 0x52d0,
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TFA9874_BF_SLOPESET = 0x52e0,
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TFA9874_BF_TDMDCG = 0x6123,
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TFA9874_BF_TDMSPKG = 0x6163,
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TFA9874_BF_LNMODE = 0x62e1,
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TFA9874_BF_LPM1MODE = 0x64e1,
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TFA9874_BF_TDMSRCMAP = 0x6802,
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TFA9874_BF_TDMSRCAS = 0x6831,
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TFA9874_BF_TDMSRCBS = 0x6851,
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TFA9874_BF_TDMSRCACLIP = 0x6871,
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TFA9874_BF_TDMSRCBCLIP = 0x6891,
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TFA9874_BF_LP1 = 0x6e10,
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TFA9874_BF_LA = 0x6e20,
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TFA9874_BF_VDDPH = 0x6e30,
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TFA9874_BF_DELCURCOMP = 0x6f02,
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TFA9874_BF_SIGCURCOMP = 0x6f40,
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TFA9874_BF_ENCURCOMP = 0x6f50,
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TFA9874_BF_LVLCLPPWM = 0x6f72,
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TFA9874_BF_DCMCC = 0x7033,
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TFA9874_BF_DCCV = 0x7071,
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TFA9874_BF_DCIE = 0x7090,
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TFA9874_BF_DCSR = 0x70a0,
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TFA9874_BF_DCDIS = 0x70e0,
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TFA9874_BF_DCPWM = 0x70f0,
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TFA9874_BF_DCTRACK = 0x7430,
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TFA9874_BF_DCTRIP = 0x7444,
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TFA9874_BF_DCHOLD = 0x7494,
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TFA9874_BF_DCINT = 0x74e0,
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TFA9874_BF_DCTRIP2 = 0x7534,
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TFA9874_BF_DCTRIPT = 0x7584,
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TFA9874_BF_DCTRIPHYSTE = 0x75f0,
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TFA9874_BF_DCVOF = 0x7635,
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TFA9874_BF_DCVOS = 0x7695,
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TFA9874_BF_MTPK = 0xa107,
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TFA9874_BF_KEY1LOCKED = 0xa200,
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TFA9874_BF_KEY2LOCKED = 0xa210,
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TFA9874_BF_CIMTP = 0xa360,
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TFA9874_BF_MTPRDMSB = 0xa50f,
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TFA9874_BF_MTPRDLSB = 0xa60f,
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TFA9874_BF_EXTTS = 0xb108,
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TFA9874_BF_TROS = 0xb190,
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TFA9874_BF_SWPROFIL = 0xee0f,
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TFA9874_BF_SWVSTEP = 0xef0f,
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TFA9874_BF_MTPOTC = 0xf000,
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TFA9874_BF_MTPEX = 0xf010,
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TFA9874_BF_DCMCCAPI = 0xf020,
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TFA9874_BF_DCMCCSB = 0xf030,
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TFA9874_BF_USERDEF = 0xf042,
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TFA9874_BF_CUSTINFO = 0xf078,
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TFA9874_BF_R25C = 0xf50f,
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};
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#define TFA9874_NAMETABLE \
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static struct TfaBfName Tfa9874DatasheetNames[] = { \
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{ 0x0, "PWDN" }, \
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{ 0x10, "I2CR" }, \
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{ 0x30, "AMPE" }, \
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{ 0x40, "DCA" }, \
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{ 0x71, "INTP" }, \
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{ 0xb0, "BYPOCP" }, \
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{ 0xc0, "TSTOCP" }, \
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{ 0x120, "MANSCONF" }, \
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{ 0x140, "MANAOOSC" }, \
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{ 0x1d0, "MUTETO" }, \
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{ 0x1e0, "OPENMTP" }, \
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{ 0x203, "AUDFS" }, \
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{ 0x240, "INPLEV" }, \
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{ 0x255, "FRACTDEL" }, \
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{ 0x30f, "REV" }, \
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{ 0x401, "REFCKEXT" }, \
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{ 0x420, "REFCKSEL" }, \
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{ 0x5c0, "SSFAIME" }, \
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{ 0x802, "AMPOCRT" }, \
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{ 0x1000, "VDDS" }, \
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{ 0x1010, "DCOCPOK" }, \
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{ 0x1020, "OTDS" }, \
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{ 0x1030, "OCDS" }, \
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{ 0x1040, "UVDS" }, \
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{ 0x1050, "MANALARM" }, \
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{ 0x1060, "TDMERR" }, \
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{ 0x1070, "NOCLK" }, \
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{ 0x1100, "DCIL" }, \
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{ 0x1110, "DCDCA" }, \
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{ 0x1130, "DCHVBAT" }, \
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{ 0x1140, "DCH114" }, \
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{ 0x1150, "DCH107" }, \
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{ 0x1160, "PLLS" }, \
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{ 0x1170, "CLKS" }, \
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{ 0x1180, "TDMLUTER" }, \
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{ 0x1192, "TDMSTAT" }, \
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{ 0x11c0, "MTPB" }, \
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{ 0x11d0, "SWS" }, \
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{ 0x11e0, "AMPS" }, \
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{ 0x11f0, "AREFS" }, \
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{ 0x1300, "OCPOAP" }, \
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{ 0x1310, "OCPOAN" }, \
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{ 0x1320, "OCPOBP" }, \
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{ 0x1330, "OCPOBN" }, \
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{ 0x1380, "OVDS" }, \
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{ 0x1390, "CLIPS" }, \
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{ 0x13a0, "ADCCR" }, \
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{ 0x13c0, "MANWAIT1" }, \
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{ 0x13e0, "MANMUTE" }, \
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{ 0x13f0, "MANOPER" }, \
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{ 0x1420, "CLKOOR" }, \
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{ 0x1433, "MANSTATE" }, \
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{ 0x1471, "DCMODE" }, \
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{ 0x1509, "BATS" }, \
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{ 0x1608, "TEMPS" }, \
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{ 0x1709, "VDDPS" }, \
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{ 0x2040, "TDME" }, \
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{ 0x2050, "TDMMODE" }, \
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{ 0x2060, "TDMCLINV" }, \
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{ 0x2073, "TDMFSLN" }, \
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{ 0x20b0, "TDMFSPOL" }, \
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{ 0x20c3, "TDMNBCK" }, \
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{ 0x2103, "TDMSLOTS" }, \
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{ 0x2144, "TDMSLLN" }, \
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{ 0x2194, "TDMBRMG" }, \
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{ 0x21e0, "TDMDEL" }, \
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{ 0x21f0, "TDMADJ" }, \
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{ 0x2201, "TDMOOMP" }, \
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{ 0x2224, "TDMSSIZE" }, \
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{ 0x2271, "TDMTXDFO" }, \
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{ 0x2291, "TDMTXUS0" }, \
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{ 0x2300, "TDMSPKE" }, \
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{ 0x2310, "TDMDCE" }, \
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{ 0x2330, "TDMCSE" }, \
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{ 0x2340, "TDMVSE" }, \
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{ 0x2603, "TDMSPKS" }, \
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{ 0x2643, "TDMDCS" }, \
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{ 0x26c3, "TDMCSS" }, \
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{ 0x2703, "TDMVSS" }, \
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{ 0x4000, "ISTVDDS" }, \
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{ 0x4010, "ISTBSTOC" }, \
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{ 0x4020, "ISTOTDS" }, \
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{ 0x4030, "ISTOCPR" }, \
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{ 0x4040, "ISTUVDS" }, \
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{ 0x4050, "ISTMANALARM" }, \
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{ 0x4060, "ISTTDMER" }, \
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{ 0x4070, "ISTNOCLK" }, \
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{ 0x4400, "ICLVDDS" }, \
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{ 0x4410, "ICLBSTOC" }, \
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{ 0x4420, "ICLOTDS" }, \
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{ 0x4430, "ICLOCPR" }, \
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{ 0x4440, "ICLUVDS" }, \
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{ 0x4450, "ICLMANALARM" }, \
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{ 0x4460, "ICLTDMER" }, \
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{ 0x4470, "ICLNOCLK" }, \
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{ 0x4800, "IEVDDS" }, \
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{ 0x4810, "IEBSTOC" }, \
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{ 0x4820, "IEOTDS" }, \
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{ 0x4830, "IEOCPR" }, \
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{ 0x4840, "IEUVDS" }, \
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{ 0x4850, "IEMANALARM" }, \
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{ 0x4860, "IETDMER" }, \
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{ 0x4870, "IENOCLK" }, \
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{ 0x4c00, "IPOVDDS" }, \
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{ 0x4c10, "IPOBSTOC" }, \
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{ 0x4c20, "IPOOTDS" }, \
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{ 0x4c30, "IPOOCPR" }, \
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{ 0x4c40, "IPOUVDS" }, \
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{ 0x4c50, "IPOMANALARM" }, \
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{ 0x4c60, "IPOTDMER" }, \
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{ 0x4c70, "IPONOCLK" }, \
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{ 0x5001, "BSSCR" }, \
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{ 0x5023, "BSST" }, \
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{ 0x5061, "BSSRL" }, \
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{ 0x5080, "VBATFLTL" }, \
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{ 0x50e0, "BSSR" }, \
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{ 0x50f0, "BSSBY" }, \
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{ 0x5100, "BSSS" }, \
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{ 0x5150, "HPFBYP" }, \
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{ 0x5170, "DPSA" }, \
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{ 0x5222, "CLIPCTRL" }, \
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{ 0x5257, "AMPGAIN" }, \
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{ 0x52d0, "SLOPEE" }, \
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{ 0x52e0, "SLOPESET" }, \
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{ 0x6123, "TDMDCG" }, \
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{ 0x6163, "TDMSPKG" }, \
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{ 0x62e1, "LNMODE" }, \
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{ 0x64e1, "LPM1MODE" }, \
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{ 0x6802, "TDMSRCMAP" }, \
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{ 0x6831, "TDMSRCAS" }, \
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{ 0x6851, "TDMSRCBS" }, \
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{ 0x6871, "TDMSRCACLIP" }, \
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{ 0x6891, "TDMSRCBCLIP" }, \
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{ 0x6e10, "LP1" }, \
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{ 0x6e20, "LA" }, \
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{ 0x6e30, "VDDPH" }, \
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{ 0x6f02, "DELCURCOMP" }, \
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{ 0x6f40, "SIGCURCOMP" }, \
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{ 0x6f50, "ENCURCOMP" }, \
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{ 0x6f72, "LVLCLPPWM" }, \
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{ 0x7033, "DCMCC" }, \
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{ 0x7071, "DCCV" }, \
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{ 0x7090, "DCIE" }, \
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{ 0x70a0, "DCSR" }, \
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{ 0x70e0, "DCDIS" }, \
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{ 0x70f0, "DCPWM" }, \
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{ 0x7430, "DCTRACK" }, \
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{ 0x7444, "DCTRIP" }, \
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{ 0x7494, "DCHOLD" }, \
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{ 0x74e0, "DCINT" }, \
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{ 0x7534, "DCTRIP2" }, \
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{ 0x7584, "DCTRIPT" }, \
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{ 0x75f0, "DCTRIPHYSTE" }, \
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{ 0x7635, "DCVOF" }, \
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{ 0x7695, "DCVOS" }, \
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{ 0xa107, "MTPK" }, \
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{ 0xa200, "KEY1LOCKED" }, \
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{ 0xa210, "KEY2LOCKED" }, \
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{ 0xa360, "CIMTP" }, \
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{ 0xa50f, "MTPRDMSB" }, \
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{ 0xa60f, "MTPRDLSB" }, \
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{ 0xb108, "EXTTS" }, \
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{ 0xb190, "TROS" }, \
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{ 0xee0f, "SWPROFIL" }, \
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{ 0xef0f, "SWVSTEP" }, \
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{ 0xf000, "MTPOTC" }, \
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{ 0xf010, "MTPEX" }, \
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{ 0xf020, "DCMCCAPI" }, \
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{ 0xf030, "DCMCCSB" }, \
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{ 0xf042, "USERDEF" }, \
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{ 0xf078, "CUSTINFO" }, \
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{ 0xf50f, "R25C" }, \
|
|
{ 0xffff, "Unknown bitfield enum" } \
|
|
}
|
|
#define TFA9874_BITNAMETABLE \
|
|
static struct TfaBfName Tfa9874BitNames[] = { \
|
|
{ 0x0, "powerdown" }, \
|
|
{ 0x10, "reset" }, \
|
|
{ 0x30, "enbl_amplifier" }, \
|
|
{ 0x40, "enbl_boost" }, \
|
|
{ 0x71, "int_pad_io" }, \
|
|
{ 0xb0, "bypass_ocp" }, \
|
|
{ 0xc0, "test_ocp" }, \
|
|
{ 0x120, "src_set_configured" }, \
|
|
{ 0x140, "enbl_osc1m_auto_off" }, \
|
|
{ 0x1d0, "disable_mute_time_out" }, \
|
|
{ 0x1e0, "unprotect_faim" }, \
|
|
{ 0x203, "audio_fs" }, \
|
|
{ 0x240, "input_level" }, \
|
|
{ 0x255, "cs_frac_delay" }, \
|
|
{ 0x2d0, "sel_hysteresis" }, \
|
|
{ 0x30f, "device_rev" }, \
|
|
{ 0x401, "pll_clkin_sel" }, \
|
|
{ 0x420, "pll_clkin_sel_osc" }, \
|
|
{ 0x5c0, "enbl_faim_ss" }, \
|
|
{ 0x802, "ctrl_on2off_criterion" }, \
|
|
{ 0xe07, "ctrl_digtoana" }, \
|
|
{ 0xf0f, "hidden_code" }, \
|
|
{ 0x1000, "flag_por" }, \
|
|
{ 0x1010, "flag_bst_ocpok" }, \
|
|
{ 0x1020, "flag_otpok" }, \
|
|
{ 0x1030, "flag_ocp_alarm" }, \
|
|
{ 0x1040, "flag_uvpok" }, \
|
|
{ 0x1050, "flag_man_alarm_state" }, \
|
|
{ 0x1060, "flag_tdm_error" }, \
|
|
{ 0x1070, "flag_lost_clk" }, \
|
|
{ 0x1100, "flag_bst_bstcur" }, \
|
|
{ 0x1110, "flag_bst_hiz" }, \
|
|
{ 0x1120, "flag_bst_peakcur" }, \
|
|
{ 0x1130, "flag_bst_voutcomp" }, \
|
|
{ 0x1140, "flag_bst_voutcomp86" }, \
|
|
{ 0x1150, "flag_bst_voutcomp93" }, \
|
|
{ 0x1160, "flag_pll_lock" }, \
|
|
{ 0x1170, "flag_clocks_stable" }, \
|
|
{ 0x1180, "flag_tdm_lut_error" }, \
|
|
{ 0x1192, "flag_tdm_status" }, \
|
|
{ 0x11c0, "flag_mtp_busy" }, \
|
|
{ 0x11d0, "flag_engage" }, \
|
|
{ 0x11e0, "flag_enbl_amp" }, \
|
|
{ 0x11f0, "flag_enbl_ref" }, \
|
|
{ 0x1300, "flag_ocpokap" }, \
|
|
{ 0x1310, "flag_ocpokan" }, \
|
|
{ 0x1320, "flag_ocpokbp" }, \
|
|
{ 0x1330, "flag_ocpokbn" }, \
|
|
{ 0x1380, "flag_ovpok" }, \
|
|
{ 0x1390, "flag_clip" }, \
|
|
{ 0x13a0, "flag_adc10_ready" }, \
|
|
{ 0x13c0, "flag_man_wait_src_settings" }, \
|
|
{ 0x13e0, "flag_man_start_mute_audio" }, \
|
|
{ 0x13f0, "flag_man_operating_state" }, \
|
|
{ 0x1420, "flag_clk_out_of_range" }, \
|
|
{ 0x1433, "man_state" }, \
|
|
{ 0x1471, "status_bst_mode" }, \
|
|
{ 0x1509, "bat_adc" }, \
|
|
{ 0x1608, "temp_adc" }, \
|
|
{ 0x1709, "vddp_adc" }, \
|
|
{ 0x2040, "tdm_enable" }, \
|
|
{ 0x2050, "tdm_mode" }, \
|
|
{ 0x2060, "tdm_clk_inversion" }, \
|
|
{ 0x2073, "tdm_fs_ws_length" }, \
|
|
{ 0x20b0, "tdm_fs_ws_polarity" }, \
|
|
{ 0x20c3, "tdm_nbck" }, \
|
|
{ 0x2103, "tdm_nb_of_slots" }, \
|
|
{ 0x2144, "tdm_slot_length" }, \
|
|
{ 0x2194, "tdm_bits_remaining" }, \
|
|
{ 0x21e0, "tdm_data_delay" }, \
|
|
{ 0x21f0, "tdm_data_adjustment" }, \
|
|
{ 0x2201, "tdm_audio_sample_compression" }, \
|
|
{ 0x2224, "tdm_sample_size" }, \
|
|
{ 0x2271, "tdm_txdata_format" }, \
|
|
{ 0x2291, "tdm_txdata_format_unused_slot_sd0" }, \
|
|
{ 0x2300, "tdm_sink0_enable" }, \
|
|
{ 0x2310, "tdm_sink1_enable" }, \
|
|
{ 0x2330, "tdm_source0_enable" }, \
|
|
{ 0x2340, "tdm_source1_enable" }, \
|
|
{ 0x2603, "tdm_sink0_slot" }, \
|
|
{ 0x2643, "tdm_sink1_slot" }, \
|
|
{ 0x26c3, "tdm_source0_slot" }, \
|
|
{ 0x2703, "tdm_source1_slot" }, \
|
|
{ 0x4000, "int_out_flag_por" }, \
|
|
{ 0x4010, "int_out_flag_bst_ocpok" }, \
|
|
{ 0x4020, "int_out_flag_otpok" }, \
|
|
{ 0x4030, "int_out_flag_ocp_alarm" }, \
|
|
{ 0x4040, "int_out_flag_uvpok" }, \
|
|
{ 0x4050, "int_out_flag_man_alarm_state" }, \
|
|
{ 0x4060, "int_out_flag_tdm_error" }, \
|
|
{ 0x4070, "int_out_flag_lost_clk" }, \
|
|
{ 0x4400, "int_in_flag_por" }, \
|
|
{ 0x4410, "int_in_flag_bst_ocpok" }, \
|
|
{ 0x4420, "int_in_flag_otpok" }, \
|
|
{ 0x4430, "int_in_flag_ocp_alarm" }, \
|
|
{ 0x4440, "int_in_flag_uvpok" }, \
|
|
{ 0x4450, "int_in_flag_man_alarm_state" }, \
|
|
{ 0x4460, "int_in_flag_tdm_error" }, \
|
|
{ 0x4470, "int_in_flag_lost_clk" }, \
|
|
{ 0x4800, "int_enable_flag_por" }, \
|
|
{ 0x4810, "int_enable_flag_bst_ocpok" }, \
|
|
{ 0x4820, "int_enable_flag_otpok" }, \
|
|
{ 0x4830, "int_enable_flag_ocp_alarm" }, \
|
|
{ 0x4840, "int_enable_flag_uvpok" }, \
|
|
{ 0x4850, "int_enable_flag_man_alarm_state" }, \
|
|
{ 0x4860, "int_enable_flag_tdm_error" }, \
|
|
{ 0x4870, "int_enable_flag_lost_clk" }, \
|
|
{ 0x4c00, "int_polarity_flag_por" }, \
|
|
{ 0x4c10, "int_polarity_flag_bst_ocpok" }, \
|
|
{ 0x4c20, "int_polarity_flag_otpok" }, \
|
|
{ 0x4c30, "int_polarity_flag_ocp_alarm" }, \
|
|
{ 0x4c40, "int_polarity_flag_uvpok" }, \
|
|
{ 0x4c50, "int_polarity_flag_man_alarm_state" }, \
|
|
{ 0x4c60, "int_polarity_flag_tdm_error" }, \
|
|
{ 0x4c70, "int_polarity_flag_lost_clk" }, \
|
|
{ 0x5001, "vbat_prot_attack_time" }, \
|
|
{ 0x5023, "vbat_prot_thlevel" }, \
|
|
{ 0x5061, "vbat_prot_max_reduct" }, \
|
|
{ 0x5080, "vbat_flt_limit" }, \
|
|
{ 0x50d0, "rst_min_vbat" }, \
|
|
{ 0x50e0, "sel_vbat" }, \
|
|
{ 0x50f0, "bypass_clipper" }, \
|
|
{ 0x5100, "batsense_steepness" }, \
|
|
{ 0x5150, "bypass_hp" }, \
|
|
{ 0x5170, "enbl_dpsa" }, \
|
|
{ 0x5222, "ctrl_cc" }, \
|
|
{ 0x5257, "gain" }, \
|
|
{ 0x52d0, "ctrl_slopectrl" }, \
|
|
{ 0x52e0, "ctrl_slope" }, \
|
|
{ 0x5301, "dpsa_level" }, \
|
|
{ 0x5321, "dpsa_release" }, \
|
|
{ 0x5340, "clipfast" }, \
|
|
{ 0x5350, "bypass_lp" }, \
|
|
{ 0x5400, "first_order_mode" }, \
|
|
{ 0x5410, "bypass_ctrlloop" }, \
|
|
{ 0x5430, "icomp_engage" }, \
|
|
{ 0x5440, "ctrl_kickback" }, \
|
|
{ 0x5450, "icomp_engage_overrule" }, \
|
|
{ 0x5503, "ctrl_dem" }, \
|
|
{ 0x5543, "ctrl_dem_mismatch" }, \
|
|
{ 0x5582, "dpsa_drive" }, \
|
|
{ 0x5690, "sel_pwm_delay_src" }, \
|
|
{ 0x56a1, "enbl_odd_up_even_down" }, \
|
|
{ 0x570a, "enbl_amp" }, \
|
|
{ 0x57b0, "enbl_engage" }, \
|
|
{ 0x57c0, "enbl_engage_pst" }, \
|
|
{ 0x5810, "hard_mute" }, \
|
|
{ 0x5820, "pwm_shape" }, \
|
|
{ 0x5844, "pwm_delay" }, \
|
|
{ 0x5890, "reclock_pwm" }, \
|
|
{ 0x58a0, "reclock_voltsense" }, \
|
|
{ 0x58c0, "enbl_pwm_phase_shift" }, \
|
|
{ 0x6123, "ctrl_attl" }, \
|
|
{ 0x6163, "ctrl_attr" }, \
|
|
{ 0x6265, "zero_lvl" }, \
|
|
{ 0x62c1, "ctrl_fb_resistor" }, \
|
|
{ 0x62e1, "lownoisegain_mode" }, \
|
|
{ 0x6305, "threshold_lvl" }, \
|
|
{ 0x6365, "hold_time" }, \
|
|
{ 0x6405, "lpm1_cal_offset" }, \
|
|
{ 0x6465, "lpm1_zero_lvl" }, \
|
|
{ 0x64e1, "lpm1_mode" }, \
|
|
{ 0x6505, "lpm1_threshold_lvl" }, \
|
|
{ 0x6565, "lpm1_hold_time" }, \
|
|
{ 0x65c0, "disable_low_power_mode" }, \
|
|
{ 0x6600, "dcdc_pfm20khz_limit" }, \
|
|
{ 0x6611, "dcdc_ctrl_maxzercnt" }, \
|
|
{ 0x6656, "dcdc_vbat_delta_detect" }, \
|
|
{ 0x66c0, "dcdc_ignore_vbat" }, \
|
|
{ 0x6700, "enbl_minion" }, \
|
|
{ 0x6713, "vth_vddpvbat" }, \
|
|
{ 0x6750, "lpen_vddpvbat" }, \
|
|
{ 0x6761, "ctrl_rfb" }, \
|
|
{ 0x6802, "tdm_source_mapping" }, \
|
|
{ 0x6831, "tdm_sourcea_frame_sel" }, \
|
|
{ 0x6851, "tdm_sourceb_frame_sel" }, \
|
|
{ 0x6871, "tdm_source0_clip_sel" }, \
|
|
{ 0x6891, "tdm_source1_clip_sel" }, \
|
|
{ 0x6a02, "rst_min_vbat_delay" }, \
|
|
{ 0x6b00, "disable_auto_engage" }, \
|
|
{ 0x6b10, "disable_engage" }, \
|
|
{ 0x6c02, "ns_hp2ln_criterion" }, \
|
|
{ 0x6c32, "ns_ln2hp_criterion" }, \
|
|
{ 0x6c69, "spare_out" }, \
|
|
{ 0x6d0f, "spare_in" }, \
|
|
{ 0x6e10, "flag_lp_detect_mode1" }, \
|
|
{ 0x6e20, "flag_low_amplitude" }, \
|
|
{ 0x6e30, "flag_vddp_gt_vbat" }, \
|
|
{ 0x6f02, "cursense_comp_delay" }, \
|
|
{ 0x6f40, "cursense_comp_sign" }, \
|
|
{ 0x6f50, "enbl_cursense_comp" }, \
|
|
{ 0x6f72, "pwms_clip_lvl" }, \
|
|
{ 0x7033, "boost_cur" }, \
|
|
{ 0x7071, "bst_slpcmplvl" }, \
|
|
{ 0x7090, "boost_intel" }, \
|
|
{ 0x70a0, "boost_speed" }, \
|
|
{ 0x70e0, "dcdcoff_mode" }, \
|
|
{ 0x70f0, "dcdc_pwmonly" }, \
|
|
{ 0x7104, "bst_drive" }, \
|
|
{ 0x7151, "bst_scalecur" }, \
|
|
{ 0x7174, "bst_slopecur" }, \
|
|
{ 0x71c1, "bst_slope" }, \
|
|
{ 0x71e0, "bst_bypass_bstcur" }, \
|
|
{ 0x71f0, "bst_bypass_bstfoldback" }, \
|
|
{ 0x7200, "enbl_bst_engage" }, \
|
|
{ 0x7210, "enbl_bst_hizcom" }, \
|
|
{ 0x7220, "enbl_bst_peak2avg" }, \
|
|
{ 0x7230, "enbl_bst_peakcur" }, \
|
|
{ 0x7240, "enbl_bst_power" }, \
|
|
{ 0x7250, "enbl_bst_slopecur" }, \
|
|
{ 0x7260, "enbl_bst_voutcomp" }, \
|
|
{ 0x7270, "enbl_bst_voutcomp86" }, \
|
|
{ 0x7280, "enbl_bst_voutcomp93" }, \
|
|
{ 0x7290, "enbl_bst_windac" }, \
|
|
{ 0x72a5, "bst_windac" }, \
|
|
{ 0x7300, "boost_alg" }, \
|
|
{ 0x7311, "boost_loopgain" }, \
|
|
{ 0x7331, "bst_freq" }, \
|
|
{ 0x7360, "bst_use_new_zercur_detect" }, \
|
|
{ 0x7430, "boost_track" }, \
|
|
{ 0x7444, "boost_trip_lvl_1st" }, \
|
|
{ 0x7494, "boost_hold_time" }, \
|
|
{ 0x74e0, "sel_dcdc_envelope_8fs" }, \
|
|
{ 0x74f0, "ignore_flag_voutcomp86" }, \
|
|
{ 0x7534, "boost_trip_lvl_2nd" }, \
|
|
{ 0x7584, "boost_trip_lvl_track" }, \
|
|
{ 0x75f0, "enbl_trip_hyst" }, \
|
|
{ 0x7635, "frst_boost_voltage" }, \
|
|
{ 0x7695, "scnd_boost_voltage" }, \
|
|
{ 0x8001, "sel_clk_cs" }, \
|
|
{ 0x8021, "micadc_speed" }, \
|
|
{ 0x8050, "cs_gain_control" }, \
|
|
{ 0x8060, "cs_bypass_gc" }, \
|
|
{ 0x8087, "cs_gain" }, \
|
|
{ 0x8210, "invertpwm" }, \
|
|
{ 0x8305, "cs_ktemp" }, \
|
|
{ 0x8364, "cs_ktemp2" }, \
|
|
{ 0x8400, "cs_adc_bsoinv" }, \
|
|
{ 0x8421, "cs_adc_hifreq" }, \
|
|
{ 0x8440, "cs_adc_nortz" }, \
|
|
{ 0x8453, "cs_adc_offset" }, \
|
|
{ 0x8490, "cs_adc_slowdel" }, \
|
|
{ 0x84a4, "cs_adc_gain" }, \
|
|
{ 0x8500, "cs_resonator_enable" }, \
|
|
{ 0x8510, "cs_classd_tran_skip" }, \
|
|
{ 0x8530, "cs_inn_short" }, \
|
|
{ 0x8540, "cs_inp_short" }, \
|
|
{ 0x8550, "cs_ldo_bypass" }, \
|
|
{ 0x8560, "cs_ldo_pulldown" }, \
|
|
{ 0x8574, "cs_ldo_voset" }, \
|
|
{ 0x8700, "enbl_cs_adc" }, \
|
|
{ 0x8710, "enbl_cs_inn1" }, \
|
|
{ 0x8720, "enbl_cs_inn2" }, \
|
|
{ 0x8730, "enbl_cs_inp1" }, \
|
|
{ 0x8740, "enbl_cs_inp2" }, \
|
|
{ 0x8750, "enbl_cs_ldo" }, \
|
|
{ 0x8780, "enbl_cs_vbatldo" }, \
|
|
{ 0x8790, "enbl_dc_filter" }, \
|
|
{ 0x8801, "volsense_pwm_sel" }, \
|
|
{ 0x8850, "vs_gain_control" }, \
|
|
{ 0x8860, "vs_bypass_gc" }, \
|
|
{ 0x8870, "vs_igen_supply" }, \
|
|
{ 0x8887, "vs_gain" }, \
|
|
{ 0x8c00, "vs_adc_bsoinv" }, \
|
|
{ 0x8c40, "vs_adc_nortz" }, \
|
|
{ 0x8c90, "vs_adc_slowdel" }, \
|
|
{ 0x8d10, "vs_classd_tran_skip" }, \
|
|
{ 0x8d30, "vs_inn_short" }, \
|
|
{ 0x8d40, "vs_inp_short" }, \
|
|
{ 0x8d50, "vs_ldo_bypass" }, \
|
|
{ 0x8d60, "vs_ldo_pulldown" }, \
|
|
{ 0x8d74, "vs_ldo_voset" }, \
|
|
{ 0x8f00, "enbl_vs_adc" }, \
|
|
{ 0x8f10, "enbl_vs_inn1" }, \
|
|
{ 0x8f20, "enbl_vs_inn2" }, \
|
|
{ 0x8f30, "enbl_vs_inp1" }, \
|
|
{ 0x8f40, "enbl_vs_inp2" }, \
|
|
{ 0x8f50, "enbl_vs_ldo" }, \
|
|
{ 0x8f80, "enbl_vs_vbatldo" }, \
|
|
{ 0xa007, "mtpkey1" }, \
|
|
{ 0xa107, "mtpkey2" }, \
|
|
{ 0xa200, "key01_locked" }, \
|
|
{ 0xa210, "key02_locked" }, \
|
|
{ 0xa302, "mtp_man_address_in" }, \
|
|
{ 0xa330, "man_copy_mtp_to_iic" }, \
|
|
{ 0xa340, "man_copy_iic_to_mtp" }, \
|
|
{ 0xa350, "auto_copy_mtp_to_iic" }, \
|
|
{ 0xa360, "auto_copy_iic_to_mtp" }, \
|
|
{ 0xa400, "faim_set_clkws" }, \
|
|
{ 0xa410, "faim_sel_evenrows" }, \
|
|
{ 0xa420, "faim_sel_oddrows" }, \
|
|
{ 0xa430, "faim_program_only" }, \
|
|
{ 0xa440, "faim_erase_only" }, \
|
|
{ 0xa50f, "mtp_man_data_out_msb" }, \
|
|
{ 0xa60f, "mtp_man_data_out_lsb" }, \
|
|
{ 0xa70f, "mtp_man_data_in_msb" }, \
|
|
{ 0xa80f, "mtp_man_data_in_lsb" }, \
|
|
{ 0xb010, "bypass_ocpcounter" }, \
|
|
{ 0xb020, "bypass_glitchfilter" }, \
|
|
{ 0xb030, "bypass_ovp" }, \
|
|
{ 0xb040, "bypass_uvp" }, \
|
|
{ 0xb050, "bypass_otp" }, \
|
|
{ 0xb060, "bypass_lost_clk" }, \
|
|
{ 0xb070, "ctrl_vpalarm" }, \
|
|
{ 0xb087, "ocp_threshold" }, \
|
|
{ 0xb108, "ext_temp" }, \
|
|
{ 0xb190, "ext_temp_sel" }, \
|
|
{ 0xc000, "use_direct_ctrls" }, \
|
|
{ 0xc010, "rst_datapath" }, \
|
|
{ 0xc020, "rst_cgu" }, \
|
|
{ 0xc038, "enbl_ref" }, \
|
|
{ 0xc0c0, "use_direct_vs_ctrls" }, \
|
|
{ 0xc0d0, "enbl_ringo" }, \
|
|
{ 0xc0e0, "use_direct_clk_ctrl" }, \
|
|
{ 0xc0f0, "use_direct_pll_ctrl" }, \
|
|
{ 0xc100, "enbl_tsense" }, \
|
|
{ 0xc110, "tsense_hibias" }, \
|
|
{ 0xc120, "enbl_flag_vbg" }, \
|
|
{ 0xc20f, "abist_offset" }, \
|
|
{ 0xc300, "bypasslatch" }, \
|
|
{ 0xc311, "sourcea" }, \
|
|
{ 0xc331, "sourceb" }, \
|
|
{ 0xc350, "inverta" }, \
|
|
{ 0xc360, "invertb" }, \
|
|
{ 0xc374, "pulselength" }, \
|
|
{ 0xc3c0, "tdm_enable_loopback" }, \
|
|
{ 0xc400, "bst_bypasslatch" }, \
|
|
{ 0xc411, "bst_source" }, \
|
|
{ 0xc430, "bst_invertb" }, \
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|
{ 0xc444, "bst_pulselength" }, \
|
|
{ 0xc490, "test_bst_ctrlsthv" }, \
|
|
{ 0xc4a0, "test_bst_iddq" }, \
|
|
{ 0xc4b0, "test_bst_rdson" }, \
|
|
{ 0xc4c0, "test_bst_cvi" }, \
|
|
{ 0xc4d0, "test_bst_ocp" }, \
|
|
{ 0xc4e0, "test_bst_sense" }, \
|
|
{ 0xc500, "test_cvi" }, \
|
|
{ 0xc510, "test_discrete" }, \
|
|
{ 0xc520, "test_iddq" }, \
|
|
{ 0xc540, "test_rdson" }, \
|
|
{ 0xc550, "test_sdelta" }, \
|
|
{ 0xc570, "test_enbl_cs" }, \
|
|
{ 0xc580, "test_enbl_vs" }, \
|
|
{ 0xc600, "enbl_pwm_dcc" }, \
|
|
{ 0xc613, "pwm_dcc_cnt" }, \
|
|
{ 0xc650, "enbl_ldo_stress" }, \
|
|
{ 0xc707, "digimuxa_sel" }, \
|
|
{ 0xc787, "digimuxb_sel" }, \
|
|
{ 0xc807, "digimuxc_sel" }, \
|
|
{ 0xc981, "int_ehs" }, \
|
|
{ 0xc9c0, "hs_mode" }, \
|
|
{ 0xca00, "enbl_anamux1" }, \
|
|
{ 0xca10, "enbl_anamux2" }, \
|
|
{ 0xca20, "enbl_anamux3" }, \
|
|
{ 0xca30, "enbl_anamux4" }, \
|
|
{ 0xca74, "anamux1" }, \
|
|
{ 0xcb04, "anamux2" }, \
|
|
{ 0xcb53, "anamux3" }, \
|
|
{ 0xcba3, "anamux4" }, \
|
|
{ 0xcd05, "pll_seli" }, \
|
|
{ 0xcd64, "pll_selp" }, \
|
|
{ 0xcdb3, "pll_selr" }, \
|
|
{ 0xcdf0, "pll_frm" }, \
|
|
{ 0xce09, "pll_ndec" }, \
|
|
{ 0xcea0, "pll_mdec_msb" }, \
|
|
{ 0xceb0, "enbl_pll" }, \
|
|
{ 0xcec0, "enbl_osc" }, \
|
|
{ 0xced0, "pll_bypass" }, \
|
|
{ 0xcee0, "pll_directi" }, \
|
|
{ 0xcef0, "pll_directo" }, \
|
|
{ 0xcf0f, "pll_mdec_lsb" }, \
|
|
{ 0xd006, "pll_pdec" }, \
|
|
{ 0xd10f, "tsig_freq_lsb" }, \
|
|
{ 0xd202, "tsig_freq_msb" }, \
|
|
{ 0xd230, "inject_tsig" }, \
|
|
{ 0xd283, "tsig_gain" }, \
|
|
{ 0xd300, "adc10_reset" }, \
|
|
{ 0xd311, "adc10_test" }, \
|
|
{ 0xd332, "adc10_sel" }, \
|
|
{ 0xd364, "adc10_prog_sample" }, \
|
|
{ 0xd3b0, "adc10_enbl" }, \
|
|
{ 0xd3c0, "bypass_lp_vbat" }, \
|
|
{ 0xd409, "data_adc10_tempbat" }, \
|
|
{ 0xd507, "ctrl_digtoana_hidden" }, \
|
|
{ 0xd580, "enbl_clk_out_of_range" }, \
|
|
{ 0xd621, "clkdiv_audio_sel" }, \
|
|
{ 0xd641, "clkdiv_muxa_sel" }, \
|
|
{ 0xd661, "clkdiv_muxb_sel" }, \
|
|
{ 0xd721, "datao_ehs" }, \
|
|
{ 0xd740, "bck_ehs" }, \
|
|
{ 0xd750, "datai_ehs" }, \
|
|
{ 0xd800, "source_in_testmode" }, \
|
|
{ 0xd810, "gainatt_feedback" }, \
|
|
{ 0xd822, "test_parametric_io" }, \
|
|
{ 0xd850, "ctrl_bst_clk_lp1" }, \
|
|
{ 0xd861, "test_spare_out1" }, \
|
|
{ 0xd880, "bst_dcmbst" }, \
|
|
{ 0xd8c3, "test_spare_out2" }, \
|
|
{ 0xee0f, "sw_profile" }, \
|
|
{ 0xef0f, "sw_vstep" }, \
|
|
{ 0xf000, "calibration_onetime" }, \
|
|
{ 0xf010, "calibr_ron_done" }, \
|
|
{ 0xf020, "calibr_dcdc_api_calibrate" }, \
|
|
{ 0xf030, "calibr_dcdc_delta_sign" }, \
|
|
{ 0xf042, "calibr_dcdc_delta" }, \
|
|
{ 0xf078, "calibr_speaker_info" }, \
|
|
{ 0xf105, "calibr_vout_offset" }, \
|
|
{ 0xf169, "spare_mpt1_15_6" }, \
|
|
{ 0xf203, "calibr_gain" }, \
|
|
{ 0xf245, "calibr_offset" }, \
|
|
{ 0xf2a5, "spare_mtp2_15_10" }, \
|
|
{ 0xf307, "calibr_gain_vs" }, \
|
|
{ 0xf387, "calibr_gain_cs" }, \
|
|
{ 0xf407, "spare_mtp4_15_0" }, \
|
|
{ 0xf487, "vs_trim" }, \
|
|
{ 0xf50f, "calibr_R25C_R" }, \
|
|
{ 0xf60f, "spare_mpt6_6_0" }, \
|
|
{ 0xf706, "ctrl_offset_a" }, \
|
|
{ 0xf770, "spare_mtp7_07" }, \
|
|
{ 0xf786, "ctrl_offset_b" }, \
|
|
{ 0xf7f0, "spare_mtp7_15" }, \
|
|
{ 0xf806, "htol_iic_addr" }, \
|
|
{ 0xf870, "htol_iic_addr_en" }, \
|
|
{ 0xf884, "calibr_temp_offset" }, \
|
|
{ 0xf8d2, "calibr_temp_gain" }, \
|
|
{ 0xf900, "mtp_lock_dcdcoff_mode" }, \
|
|
{ 0xf910, "spare_mtp9_1" }, \
|
|
{ 0xf920, "mtp_lock_bypass_clipper" }, \
|
|
{ 0xf930, "mtp_lock_max_dcdc_voltage" }, \
|
|
{ 0xf943, "calibr_vbg_trim" }, \
|
|
{ 0xf980, "spare_mtp9_8" }, \
|
|
{ 0xf990, "mtp_enbl_pwm_delay_clock_gating" }, \
|
|
{ 0xf9a0, "mtp_enbl_ocp_clock_gating" }, \
|
|
{ 0xf9b0, "mtp_gate_cgu_clock_for_test" }, \
|
|
{ 0xf9c0, "mtp_tdm_pad_sel" }, \
|
|
{ 0xf9d2, "spare_mtp9_15_12" }, \
|
|
{ 0xfa0f, "mtpdataA" }, \
|
|
{ 0xfb0f, "mtpdataB" }, \
|
|
{ 0xfc0f, "mtpdataC" }, \
|
|
{ 0xfd0f, "mtpdataD" }, \
|
|
{ 0xfe0f, "mtpdataE" }, \
|
|
{ 0xff07, "calibr_osc_delta_ndiv" }, \
|
|
{ 0xff87, "spare_mtp7_15_08" }, \
|
|
{ 0xffff, "Unknown bitfield enum" } \
|
|
}
|
|
enum tfa9874_irq {
|
|
tfa9874_irq_stvdds = 0,
|
|
tfa9874_irq_stbstoc = 1,
|
|
tfa9874_irq_stotds = 2,
|
|
tfa9874_irq_stocpr = 3,
|
|
tfa9874_irq_stuvds = 4,
|
|
tfa9874_irq_stmanalarm = 5,
|
|
tfa9874_irq_sttdmer = 6,
|
|
tfa9874_irq_stnoclk = 7,
|
|
tfa9874_irq_max = 8,
|
|
tfa9874_irq_all = -1
|
|
};
|
|
#define TFA9874_IRQ_NAMETABLE \
|
|
static struct TfaIrqName Tfa9874IrqNames[] = { \
|
|
{ 0, "STVDDS" }, { 1, "STBSTOC" }, { 2, "STOTDS" }, \
|
|
{ 3, "STOCPR" }, { 4, "STUVDS" }, { 5, "STMANALARM" }, \
|
|
{ 6, "STTDMER" }, { 7, "STNOCLK" }, { 8, "8" }, \
|
|
}
|
|
#endif
|