454 lines
21 KiB
C
454 lines
21 KiB
C
/*
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* Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef TFA_INC_TFA9891_TFAFIELDNAMES_H_
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#define TFA_INC_TFA9891_TFAFIELDNAMES_H_
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#define TFA9891_I2CVERSION 13
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#define TFA9891_NAMETABLE \
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static struct TfaBfName Tfa9891DatasheetNames[] = { \
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{ 0x0, "VDDS" }, { 0x10, "PLLS" }, \
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{ 0x20, "OTDS" }, { 0x30, "OVDS" }, \
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{ 0x40, "UVDS" }, { 0x50, "OCDS" }, \
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{ 0x60, "CLKS" }, { 0x70, "CLIPS" }, \
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{ 0x80, "MTPB" }, { 0x90, "DCCS" }, \
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{ 0xa0, "SPKS" }, { 0xb0, "ACS" }, \
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{ 0xc0, "SWS" }, { 0xd0, "WDS" }, \
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{ 0xe0, "AMPS" }, { 0xf0, "AREFS" }, \
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{ 0x109, "BATS" }, { 0x208, "TEMPS" }, \
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{ 0x307, "REV" }, { 0x402, "I2SF" }, \
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{ 0x431, "CHS12" }, { 0x450, "CHS3" }, \
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{ 0x461, "CHSA" }, { 0x481, "I2SDOC" }, \
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{ 0x4a0, "DISP" }, { 0x4b0, "I2SDOE" }, \
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{ 0x4c3, "I2SSR" }, { 0x501, "BSSCR" }, \
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{ 0x523, "BSST" }, { 0x561, "BSSRL" }, \
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{ 0x582, "BSSRR" }, { 0x5b1, "BSSHY" }, \
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{ 0x5e0, "BSSR" }, { 0x5f0, "BSSBY" }, \
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{ 0x600, "DPSA" }, { 0x613, "AMPSL" }, \
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{ 0x650, "CFSM" }, { 0x670, "BSSS" }, \
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{ 0x687, "VOL" }, { 0x702, "DCVO" }, \
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{ 0x732, "DCMCC" }, { 0x7a0, "DCIE" }, \
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{ 0x7b0, "DCSR" }, { 0x800, "TROS" }, \
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{ 0x818, "EXTTS" }, { 0x900, "PWDN" }, \
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{ 0x910, "I2CR" }, { 0x920, "CFE" }, \
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{ 0x930, "AMPE" }, { 0x940, "DCA" }, \
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{ 0x950, "SBSL" }, { 0x960, "AMPC" }, \
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{ 0x970, "DCDIS" }, { 0x980, "PSDR" }, \
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{ 0x991, "DCCV" }, { 0x9b1, "CCFD" }, \
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{ 0x9d0, "ISEL" }, { 0x9e0, "IPLL" }, \
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{ 0xa02, "DOLS" }, { 0xa32, "DORS" }, \
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{ 0xa62, "SPKL" }, { 0xa91, "SPKR" }, \
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{ 0xab3, "DCFG" }, { 0xb07, "MTPK" }, \
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{ 0xf00, "VDDD" }, { 0xf10, "OTDD" }, \
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{ 0xf20, "OVDD" }, { 0xf30, "UVDD" }, \
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{ 0xf40, "OCDD" }, { 0xf50, "CLKD" }, \
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{ 0xf60, "DCCD" }, { 0xf70, "SPKD" }, \
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{ 0xf80, "WDD" }, { 0xfe0, "INT" }, \
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{ 0xff0, "INTP" }, { 0x1000, "PDMSEL" }, \
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{ 0x1010, "I2SMOUTEN" }, { 0x1021, "PDMORSEL" }, \
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{ 0x1041, "PDMOLSEL" }, { 0x1061, "PADSEL" }, \
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{ 0x1100, "PDMOSDEN" }, { 0x1110, "PDMOSDCF" }, \
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{ 0x1140, "SAAMEN" }, { 0x1150, "SAAMLPEN" }, \
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{ 0x1160, "PDMOINTEN" }, { 0x1203, "PDMORG1" }, \
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{ 0x1243, "PDMORG2" }, { 0x1303, "PDMOLG1" }, \
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{ 0x1343, "PDMOLG2" }, { 0x2202, "SAAMGAIN" }, \
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{ 0x2250, "SAAMPGACTRL" }, { 0x2500, "PLLCCOSEL" }, \
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{ 0x4600, "CSBYPGC" }, { 0x4900, "CLIP" }, \
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{ 0x4910, "CLIP2" }, { 0x62b0, "CIMTP" }, \
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{ 0x7000, "RST" }, { 0x7011, "DMEM" }, \
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{ 0x7030, "AIF" }, { 0x7040, "CFINT" }, \
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{ 0x7087, "REQ" }, { 0x710f, "MADD" }, \
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{ 0x720f, "MEMA" }, { 0x7307, "ERR" }, \
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{ 0x7387, "ACK" }, { 0x8000, "MTPOTC" }, \
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{ 0x8010, "MTPEX" }, { 0x8045, "SWPROFIL" }, \
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{ 0x80a5, "SWVSTEP" }, { 0xffff, "Unknown bitfield enum" } \
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}
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#define TFA9891_BITNAMETABLE \
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static struct TfaBfName Tfa9891BitNames[] = { \
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{ 0x0, "POR" }, \
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{ 0x10, "PLL_LOCK" }, \
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{ 0x20, "flag_otpok" }, \
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{ 0x30, "flag_ovpok" }, \
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{ 0x40, "flag_uvpok" }, \
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{ 0x50, "flag_OCP_alarm" }, \
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{ 0x60, "flag_clocks_stable" }, \
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{ 0x70, "CLIP" }, \
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{ 0x80, "mtp_busy" }, \
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{ 0x90, "flag_pwrokbst" }, \
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{ 0xa0, "flag_cf_speakererror" }, \
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{ 0xb0, "flag_cold_started" }, \
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{ 0xc0, "flag_engage" }, \
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{ 0xd0, "flag_watchdog_reset" }, \
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{ 0xe0, "flag_enbl_amp" }, \
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{ 0xf0, "flag_enbl_ref" }, \
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{ 0x109, "bat_adc" }, \
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{ 0x208, "temp_adc" }, \
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{ 0x307, "rev_reg" }, \
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{ 0x402, "i2s_seti" }, \
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{ 0x431, "chan_sel1" }, \
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{ 0x450, "lr_sw_i2si2" }, \
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{ 0x461, "input_sel" }, \
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{ 0x481, "datao_sel" }, \
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{ 0x4a0, "disable_idp" }, \
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{ 0x4b0, "enbl_datao" }, \
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{ 0x4c3, "i2s_fs" }, \
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{ 0x501, "vbat_prot_attacktime" }, \
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{ 0x523, "vbat_prot_thlevel" }, \
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{ 0x561, "vbat_prot_max_reduct" }, \
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{ 0x582, "vbat_prot_release_t" }, \
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{ 0x5b1, "vbat_prot_hysterese" }, \
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{ 0x5d0, "reset_min_vbat" }, \
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{ 0x5e0, "sel_vbat" }, \
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{ 0x5f0, "bypass_clipper" }, \
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{ 0x600, "dpsa" }, \
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{ 0x613, "ctrl_slope" }, \
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{ 0x650, "cf_mute" }, \
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{ 0x660, "sel_other_vamp" }, \
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{ 0x670, "ctrl_batsensesteepness" }, \
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{ 0x687, "vol" }, \
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{ 0x702, "ctrl_bstvolt" }, \
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{ 0x732, "ctrl_bstcur" }, \
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{ 0x761, "ctrl_slopebst_1_0" }, \
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{ 0x781, "ctrl_slopebst_3_2" }, \
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{ 0x7a0, "boost_intel" }, \
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{ 0x7b0, "boost_speed" }, \
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{ 0x7c1, "ctrl_delay_comp_dcdc" }, \
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{ 0x7e0, "boost_input" }, \
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{ 0x7f0, "ctrl_supplysense" }, \
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{ 0x800, "ext_temp_sel" }, \
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{ 0x818, "ext_temp" }, \
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{ 0x8a0, "ctrl_spk_coilpvp_bst" }, \
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{ 0x8b2, "ctrl_dcdc_synchronisation" }, \
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{ 0x8e0, "ctrl_cs_samplevalid" }, \
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{ 0x900, "PowerDown" }, \
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{ 0x910, "reset" }, \
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{ 0x920, "enbl_coolflux" }, \
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{ 0x930, "enbl_amplifier" }, \
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{ 0x940, "enbl_boost" }, \
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{ 0x950, "cf_configured" }, \
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{ 0x960, "sel_enbl_amplifier" }, \
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{ 0x970, "dcdcoff_mode" }, \
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{ 0x980, "cttr_iddqtest" }, \
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{ 0x991, "ctrl_coil_value" }, \
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{ 0x9b1, "ctrl_sel_cf_clock" }, \
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{ 0x9d0, "intf_sel" }, \
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{ 0x9e0, "sel_ws_bck" }, \
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{ 0xa02, "sel_i2so_l" }, \
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{ 0xa32, "sel_i2so_r" }, \
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{ 0xa62, "ctrl_spkr_coil" }, \
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{ 0xa91, "ctrl_spr_res" }, \
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{ 0xab3, "ctrl_dcdc_spkr_i_comp_gain" }, \
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{ 0xaf0, "ctrl_dcdc_spkr_i_comp_sign" }, \
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{ 0xb07, "MTP_key2" }, \
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{ 0xc0c, "clk_sync_delay" }, \
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{ 0xcf0, "enbl_clk_sync" }, \
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{ 0xd0c, "adc_sync_delay" }, \
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{ 0xdf0, "enable_adc_sync" }, \
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{ 0xe00, "bypass_dcdc_curr_prot" }, \
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{ 0xe24, "ctrl_digtoana6_2" }, \
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{ 0xe70, "switch_on_icomp" }, \
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{ 0xe87, "reserve_reg_1_7_0" }, \
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{ 0xf00, "flag_por_mask" }, \
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{ 0xf10, "flag_otpok_mask" }, \
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{ 0xf20, "flag_ovpok_mask" }, \
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{ 0xf30, "flag_uvpok_mask" }, \
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{ 0xf40, "flag_ocp_alarm_mask" }, \
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{ 0xf50, "flag_clocks_stable_mask" }, \
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{ 0xf60, "flag_pwrokbst_mask" }, \
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{ 0xf70, "flag_cf_speakererror_mask" }, \
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{ 0xf80, "flag_watchdog_reset_mask" }, \
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{ 0xf90, "flag_lost_clk_mask" }, \
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{ 0xfe0, "enable_interrupt" }, \
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{ 0xff0, "invert_int_polarity" }, \
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{ 0x1000, "pdm_i2s_input" }, \
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{ 0x1010, "I2S_master_ena" }, \
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{ 0x1021, "pdm_out_sel_r" }, \
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{ 0x1041, "pdm_out_sel_l" }, \
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{ 0x1061, "micdat_out_sel" }, \
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{ 0x1100, "secure_dly" }, \
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{ 0x1110, "d_out_valid_rf_mux" }, \
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{ 0x1140, "Speak_As_Mic_en" }, \
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{ 0x1150, "speak_as_mic_lp_mode" }, \
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{ 0x1160, "pdm_out_rate" }, \
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{ 0x1203, "ds4_g1_r" }, \
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{ 0x1243, "ds4_g2_r" }, \
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{ 0x1303, "ds4_g1_l" }, \
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{ 0x1343, "ds4_g2_l" }, \
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{ 0x1400, "clk_secure_dly" }, \
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{ 0x1410, "data_secure_dly" }, \
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{ 0x2202, "Ctrl_saam_pga_gain" }, \
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{ 0x2250, "ctrl_saam_pga_src" }, \
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{ 0x2300, "flag_saam_spare" }, \
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{ 0x2400, "ctrl_saam_pga_tm" }, \
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{ 0x2500, "pll_fcco" }, \
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{ 0x3000, "flag_hi_small" }, \
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{ 0x3010, "flag_hi_large" }, \
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{ 0x3020, "flag_lo_small" }, \
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{ 0x3030, "flag_lo_large" }, \
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{ 0x3040, "flag_voutcomp" }, \
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{ 0x3050, "flag_voutcomp93" }, \
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{ 0x3060, "flag_voutcomp86" }, \
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{ 0x3070, "flag_hiz" }, \
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{ 0x3080, "flag_hi_peak" }, \
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{ 0x3090, "flag_ocpokbst" }, \
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{ 0x30a0, "flag_peakcur" }, \
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{ 0x30b0, "flag_ocpokap" }, \
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{ 0x30c0, "flag_ocpokan" }, \
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{ 0x30d0, "flag_ocpokbp" }, \
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{ 0x30e0, "flag_ocpokbn" }, \
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{ 0x30f0, "lost_clk" }, \
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{ 0x310f, "mtp_man_data_out" }, \
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{ 0x3200, "key01_locked" }, \
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{ 0x3210, "key02_locked" }, \
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{ 0x3225, "mtp_ecc_tcout" }, \
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{ 0x3280, "mtpctrl_valid_test_rd" }, \
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{ 0x3290, "mtpctrl_valid_test_wr" }, \
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{ 0x32a0, "flag_in_alarm_state" }, \
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{ 0x32b0, "mtp_ecc_err2" }, \
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{ 0x32c0, "mtp_ecc_err1" }, \
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{ 0x32d0, "mtp_mtp_hvf" }, \
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{ 0x32f0, "mtp_zero_check_fail" }, \
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{ 0x3300, "flag_adc10_ready" }, \
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{ 0x3310, "flag_clipa_high" }, \
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{ 0x3320, "flag_clipa_low" }, \
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{ 0x3330, "flag_clipb_high" }, \
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{ 0x3340, "flag_clipb_low" }, \
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{ 0x3359, "data_adc10_tempbat" }, \
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{ 0x33f0, "flag_vddd_comp_nok" }, \
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{ 0x400f, "hid_code" }, \
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{ 0x4100, "bypass_hp" }, \
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{ 0x4110, "hard_mute" }, \
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{ 0x4120, "soft_mute" }, \
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{ 0x4134, "PWM_Delay" }, \
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{ 0x4180, "PWM_Shape" }, \
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{ 0x4190, "PWM_BitLength" }, \
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{ 0x4207, "ctrl_drive" }, \
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{ 0x4281, "dpsalevel" }, \
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{ 0x42a1, "dpsa_release" }, \
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{ 0x42c0, "ctrl_coincidence" }, \
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{ 0x42d0, "ctrl_kickback" }, \
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{ 0x42e0, "ctrl_test_sdeltaoffset" }, \
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{ 0x42f0, "ctrl_test_sdeltaclk" }, \
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{ 0x4309, "ctrl_drivebst" }, \
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{ 0x43a0, "ctrl_ocptestbst" }, \
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{ 0x43c0, "enbl_hi_peak" }, \
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{ 0x43d0, "test_abistfft_enbl" }, \
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{ 0x43e0, "ctrl_sensetest_amp" }, \
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{ 0x43f0, "test_bcontrol" }, \
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{ 0x4400, "ctrl_reversebst" }, \
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{ 0x4410, "ctrl_sensetest" }, \
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{ 0x4420, "enbl_engagebst" }, \
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{ 0x4430, "enbl_hi_small" }, \
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{ 0x4440, "enbl_hi_large" }, \
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{ 0x4450, "enbl_lo_small" }, \
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{ 0x4460, "enbl_lo_large" }, \
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{ 0x4470, "enbl_slopecur" }, \
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{ 0x4480, "enbl_voutcomp" }, \
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{ 0x4490, "enbl_voutcomp93" }, \
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{ 0x44a0, "enbl_voutcomp86" }, \
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{ 0x44b0, "enbl_hizcom" }, \
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{ 0x44c0, "enbl_pcdac" }, \
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{ 0x44d0, "enbl_pccomp" }, \
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{ 0x44e0, "enbl_windac" }, \
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{ 0x44f0, "enbl_powerbst" }, \
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{ 0x4507, "ocp_thr" }, \
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{ 0x4580, "bypass_glitchfilter" }, \
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{ 0x4590, "bypass_ovp" }, \
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{ 0x45a0, "bypass_uvp" }, \
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{ 0x45b0, "bypass_otp" }, \
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{ 0x45c0, "bypass_ocp" }, \
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{ 0x45d0, "bypass_ocpcounter" }, \
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{ 0x45e0, "bypass_lost_clk" }, \
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{ 0x45f0, "vpalarm" }, \
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{ 0x4600, "bypass_gc" }, \
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{ 0x4610, "cs_gain_control" }, \
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{ 0x4627, "cs_gain" }, \
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{ 0x46a0, "bypass_lp" }, \
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{ 0x46b0, "bypass_pwmcounter" }, \
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{ 0x46c0, "ctrl_cs_negfixed" }, \
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{ 0x46d2, "ctrl_cs_neghyst" }, \
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{ 0x4700, "switch_fb" }, \
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{ 0x4713, "se_hyst" }, \
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{ 0x4754, "se_level" }, \
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{ 0x47a5, "ktemp" }, \
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{ 0x4800, "ctrl_negin" }, \
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{ 0x4810, "ctrl_cs_sein" }, \
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{ 0x4820, "ctrl_coincidencecs" }, \
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{ 0x4830, "ctrl_iddqtestbst" }, \
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{ 0x4840, "ctrl_coincidencebst" }, \
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{ 0x4851, "clock_sh_sel" }, \
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{ 0x4876, "delay_se_neg" }, \
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{ 0x48e1, "ctrl_cs_ttrack" }, \
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{ 0x4900, "ctrl_bypassclip" }, \
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{ 0x4910, "ctrl_bypassclip2" }, \
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{ 0x4920, "ctrl_clkgateCFoff" }, \
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{ 0x4930, "ctrl_testabst" }, \
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{ 0x4940, "ctrl_clipfast" }, \
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{ 0x4950, "ctrl_cs_8ohm" }, \
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{ 0x4960, "reserved" }, \
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{ 0x4974, "delay_clock_sh" }, \
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{ 0x49c0, "inv_clksh" }, \
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{ 0x49d0, "inv_neg" }, \
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{ 0x49e0, "inv_se" }, \
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{ 0x49f0, "setse" }, \
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{ 0x4a12, "ctrl_adc10_sel" }, \
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{ 0x4a60, "ctrl_adc10_reset" }, \
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{ 0x4a81, "ctrl_adc10_test" }, \
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{ 0x4aa0, "ctrl_bypass_lp_vbat" }, \
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{ 0x4ae0, "ctrl_dc_offset" }, \
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{ 0x4af0, "ctrl_tsense_hibias" }, \
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{ 0x4b00, "ctrl_adc13_iset" }, \
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{ 0x4b14, "ctrl_adc13_gain" }, \
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{ 0x4b61, "ctrl_adc13_slowdel" }, \
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{ 0x4b83, "ctrl_adc13_offset" }, \
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{ 0x4bc0, "ctrl_adc13_bsoinv" }, \
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{ 0x4bd0, "ctrl_adc13_resonator_enable" }, \
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{ 0x4be0, "ctrl_testmicadc" }, \
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{ 0x4c0f, "ctrl_offset" }, \
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{ 0x4d05, "ctrl_windac" }, \
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{ 0x4d65, "ctrl_peakcur" }, \
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{ 0x4dc3, "pwm_dcc_cnt" }, \
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{ 0x4e04, "ctrl_slopecur" }, \
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{ 0x4e53, "ctrl_dem" }, \
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{ 0x4e93, "ctrl_demmismatch" }, \
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{ 0x4ed0, "enbl_pwm_dcc" }, \
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{ 0x5007, "gain" }, \
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{ 0x5081, "ctrl_sourceb" }, \
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{ 0x50a1, "ctrl_sourcea" }, \
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{ 0x50c1, "ctrl_sourcebst" }, \
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{ 0x50e1, "ctrl_test_mono" }, \
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{ 0x5104, "pulselengthbst" }, \
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{ 0x5150, "ctrl_bypasslatchbst" }, \
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{ 0x5160, "invertbst" }, \
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{ 0x5174, "pulselength" }, \
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{ 0x51c0, "ctrl_bypasslatch" }, \
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{ 0x51d0, "invertb" }, \
|
|
{ 0x51e0, "inverta" }, \
|
|
{ 0x51f0, "ctrl_bypass_ctrlloop" }, \
|
|
{ 0x5200, "ctrl_test_discrete" }, \
|
|
{ 0x5210, "ctrl_test_rdsona" }, \
|
|
{ 0x5220, "ctrl_test_rdsonb" }, \
|
|
{ 0x5230, "ctrl_test_rdsonbst" }, \
|
|
{ 0x5240, "ctrl_test_cvia" }, \
|
|
{ 0x5250, "ctrl_test_cvib" }, \
|
|
{ 0x5260, "ctrl_test_cvibst" }, \
|
|
{ 0x5290, "test_bypass_pwmdiscretea" }, \
|
|
{ 0x52a0, "test_bypass_pwmdiscreteb" }, \
|
|
{ 0x52b0, "ctrl_clipc_forcehigh" }, \
|
|
{ 0x52c0, "ctrl_clipc_forcelow" }, \
|
|
{ 0x52d0, "ctrl_test_sdelta" }, \
|
|
{ 0x52e0, "ctrl_test_swhvp" }, \
|
|
{ 0x52f0, "test_gain_reduction" }, \
|
|
{ 0x5303, "ctrl_digimux_out_test1" }, \
|
|
{ 0x5343, "ctrl_digimux_out_test2" }, \
|
|
{ 0x5383, "ctrl_digimux_out_data1" }, \
|
|
{ 0x53c3, "ctrl_digimux_out_data3" }, \
|
|
{ 0x5400, "hs_mode" }, \
|
|
{ 0x5412, "test_parametric_io" }, \
|
|
{ 0x5440, "enbl_ringo" }, \
|
|
{ 0x5480, "ctrl_cliplevel" }, \
|
|
{ 0x5491, "ctrl_anamux_sel" }, \
|
|
{ 0x54b0, "test_vdddsw_dio" }, \
|
|
{ 0x54c0, "ctrl_bypass_diosw_ovp" }, \
|
|
{ 0x54d0, "test_vddd_sw" }, \
|
|
{ 0x54e0, "test_vddd_sw_comp" }, \
|
|
{ 0x550e, "enbl_amp" }, \
|
|
{ 0x55f0, "fr_fsp" }, \
|
|
{ 0x5600, "use_direct_ctrls" }, \
|
|
{ 0x5610, "rst_datapath" }, \
|
|
{ 0x5620, "rst_cgu" }, \
|
|
{ 0x5637, "enbl_ref" }, \
|
|
{ 0x56b0, "enbl_engage" }, \
|
|
{ 0x56c0, "use_direct_clk_ctrl" }, \
|
|
{ 0x56d0, "use_direct_pll_ctrl" }, \
|
|
{ 0x56e0, "use_direct_ctrls_2" }, \
|
|
{ 0x5707, "ctrl_anamux_out_test1" }, \
|
|
{ 0x5782, "ctrl_zero" }, \
|
|
{ 0x57b0, "enbl_ldo_stress" }, \
|
|
{ 0x57c0, "ctrl_ocptest" }, \
|
|
{ 0x57e0, "ctrl_otptest" }, \
|
|
{ 0x57f0, "ctrl_reverse" }, \
|
|
{ 0x5802, "pll_mdec_msb" }, \
|
|
{ 0x5833, "pll_selr" }, \
|
|
{ 0x5874, "pll_selp" }, \
|
|
{ 0x58c3, "pll_seli" }, \
|
|
{ 0x5900, "pll_psel" }, \
|
|
{ 0x5910, "use_direct_pll_psel" }, \
|
|
{ 0x5923, "nbck" }, \
|
|
{ 0x5960, "auto_nbck" }, \
|
|
{ 0x5970, "pll_frm" }, \
|
|
{ 0x5980, "pll_directi" }, \
|
|
{ 0x5990, "pll_directo" }, \
|
|
{ 0x59a0, "enbl_PLL" }, \
|
|
{ 0x59b0, "sel_clkout" }, \
|
|
{ 0x59e0, "fr_lost_clk" }, \
|
|
{ 0x59f0, "pll_bypass" }, \
|
|
{ 0x5a0f, "tsig_freq" }, \
|
|
{ 0x5b02, "tsig_freq_msb" }, \
|
|
{ 0x5b30, "inject_tsig" }, \
|
|
{ 0x5b44, "ctrl_adc10_prog_sample" }, \
|
|
{ 0x5c01, "pll_ndec_msb" }, \
|
|
{ 0x5c2d, "pll_mdec" }, \
|
|
{ 0x5d06, "pll_pdec" }, \
|
|
{ 0x5d87, "pll_ndec" }, \
|
|
{ 0x5e00, "pdm_ch_sel_reg" }, \
|
|
{ 0x5e10, "pdm_iis_rst_reg" }, \
|
|
{ 0x5e20, "clk_src_sel_reg" }, \
|
|
{ 0x5e70, "pdm_resync_bypass" }, \
|
|
{ 0x6007, "MTP_key1" }, \
|
|
{ 0x6185, "mtp_ecc_tcin" }, \
|
|
{ 0x6203, "mtp_man_address_in" }, \
|
|
{ 0x6260, "mtp_ecc_eeb" }, \
|
|
{ 0x6270, "mtp_ecc_ecb" }, \
|
|
{ 0x6280, "man_copy_mtp_to_iic" }, \
|
|
{ 0x6290, "man_copy_iic_to_mtp" }, \
|
|
{ 0x62a0, "auto_copy_mtp_to_iic" }, \
|
|
{ 0x62b0, "auto_copy_iic_to_mtp" }, \
|
|
{ 0x62d2, "mtp_speed_mode" }, \
|
|
{ 0x6340, "mtp_dircet_enable" }, \
|
|
{ 0x6350, "mtp_direct_wr" }, \
|
|
{ 0x6360, "mtp_direct_rd" }, \
|
|
{ 0x6370, "mtp_direct_rst" }, \
|
|
{ 0x6380, "mtp_direct_ers" }, \
|
|
{ 0x6390, "mtp_direct_prg" }, \
|
|
{ 0x63a0, "mtp_direct_epp" }, \
|
|
{ 0x63b4, "mtp_direct_test" }, \
|
|
{ 0x640f, "mtp_man_data_in" }, \
|
|
{ 0x7000, "cf_rst_dsp" }, \
|
|
{ 0x7011, "cf_dmem" }, \
|
|
{ 0x7030, "cf_aif" }, \
|
|
{ 0x7040, "cf_int" }, \
|
|
{ 0x7087, "cf_req" }, \
|
|
{ 0x710f, "cf_madd" }, \
|
|
{ 0x720f, "cf_mema" }, \
|
|
{ 0x7307, "cf_err" }, \
|
|
{ 0x7387, "cf_ack" }, \
|
|
{ 0x8000, "calibration_onetime" }, \
|
|
{ 0x8010, "calibr_ron_done" }, \
|
|
{ 0x8105, "calibr_vout_offset" }, \
|
|
{ 0x8163, "calibr_delta_gain" }, \
|
|
{ 0x81a5, "calibr_offs_amp" }, \
|
|
{ 0x8207, "calibr_gain_cs" }, \
|
|
{ 0x8284, "calibr_temp_offset" }, \
|
|
{ 0x82d2, "calibr_temp_gain" }, \
|
|
{ 0x830f, "calibr_ron" }, \
|
|
{ 0x8406, "ctrl_offset_a" }, \
|
|
{ 0x8486, "ctrl_offset_b" }, \
|
|
{ 0x850f, "type_bits_HW" }, \
|
|
{ 0x860f, "type_bits1_SW" }, \
|
|
{ 0x870f, "type_bits2_SW" }, \
|
|
{ 0x8a0f, "production_data1" }, \
|
|
{ 0x8b0f, "production_data2" }, \
|
|
{ 0x8c0f, "production_data3" }, \
|
|
{ 0x8d0f, "production_data4" }, \
|
|
{ 0x8e0f, "production_data5" }, \
|
|
{ 0x8f0f, "production_data6" }, \
|
|
{ 0xffff, "Unknown bitfield enum" } \
|
|
}
|
|
#endif
|