118 lines
2.7 KiB
C
118 lines
2.7 KiB
C
/*
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* skl-ssp-clk.h - Skylake ssp clock information and ipc structure
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*
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* Copyright (C) 2017 Intel Corp
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* Author: Jaikrishna Nemallapudi <jaikrishnax.nemallapudi@intel.com>
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* Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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*/
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#ifndef SOUND_SOC_SKL_SSP_CLK_H
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#define SOUND_SOC_SKL_SSP_CLK_H
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#define SKL_MAX_SSP 6
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/* xtal/cardinal/pll, parent of ssp clocks and mclk */
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#define SKL_MAX_CLK_SRC 3
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#define SKL_MAX_SSP_CLK_TYPES 3 /* mclk, sclk, sclkfs */
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#define SKL_MAX_CLK_CNT (SKL_MAX_SSP * SKL_MAX_SSP_CLK_TYPES)
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/* Max number of configurations supported for each clock */
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#define SKL_MAX_CLK_RATES 10
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#define SKL_SCLK_OFS SKL_MAX_SSP
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#define SKL_SCLKFS_OFS (SKL_SCLK_OFS + SKL_MAX_SSP)
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enum skl_clk_type {
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SKL_MCLK,
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SKL_SCLK,
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SKL_SCLK_FS,
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};
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enum skl_clk_src_type {
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SKL_XTAL,
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SKL_CARDINAL,
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SKL_PLL,
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};
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struct skl_clk_parent_src {
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u8 clk_id;
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const char *name;
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unsigned long rate;
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const char *parent_name;
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};
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struct skl_tlv_hdr {
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u32 type;
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u32 size;
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};
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struct skl_dmactrl_mclk_cfg {
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struct skl_tlv_hdr hdr;
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/* DMA Clk TLV params */
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u32 clk_warm_up:16;
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u32 mclk:1;
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u32 warm_up_over:1;
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u32 rsvd0:14;
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u32 clk_stop_delay:16;
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u32 keep_running:1;
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u32 clk_stop_over:1;
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u32 rsvd1:14;
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};
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struct skl_dmactrl_sclkfs_cfg {
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struct skl_tlv_hdr hdr;
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/* DMA SClk&FS TLV params */
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u32 sampling_frequency;
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u32 bit_depth;
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u32 channel_map;
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u32 channel_config;
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u32 interleaving_style;
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u32 number_of_channels : 8;
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u32 valid_bit_depth : 8;
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u32 sample_type : 8;
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u32 reserved : 8;
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};
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union skl_clk_ctrl_ipc {
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struct skl_dmactrl_mclk_cfg mclk;
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struct skl_dmactrl_sclkfs_cfg sclk_fs;
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};
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struct skl_clk_rate_cfg_table {
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unsigned long rate;
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union skl_clk_ctrl_ipc dma_ctl_ipc;
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void *config;
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};
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/*
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* rate for mclk will be in rates[0]. For sclk and sclkfs, rates[] store
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* all possible clocks ssp can generate for that platform.
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*/
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struct skl_ssp_clk {
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const char *name;
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const char *parent_name;
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struct skl_clk_rate_cfg_table rate_cfg[SKL_MAX_CLK_RATES];
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};
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struct skl_clk_pdata {
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struct skl_clk_parent_src *parent_clks;
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int num_clks;
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struct skl_ssp_clk *ssp_clks;
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void *pvt_data;
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};
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#endif /* SOUND_SOC_SKL_SSP_CLK_H */
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