208 lines
6.5 KiB
C
208 lines
6.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* mt6833-afe-clk.h -- Mediatek 6833 afe clock ctrl definition
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*
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* Copyright (c) 2020 MediaTek Inc.
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* Author: Eason Yen <eason.yen@mediatek.com>
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*/
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#ifndef _MT6833_AFE_CLOCK_CTRL_H_
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#define _MT6833_AFE_CLOCK_CTRL_H_
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#define AP_PLL_CON3 0x0014
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#define APLL1_CON0 0x0318
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#define APLL1_CON1 0x031c
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#define APLL1_CON2 0x0320
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#define APLL1_CON4 0x0328
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#define APLL1_TUNER_CON0 0x0040
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#define APLL2_CON0 0x032c
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#define APLL2_CON1 0x0330
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#define APLL2_CON2 0x0334
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#define APLL2_CON4 0x033c
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#define APLL2_TUNER_CON0 0x0044
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#define CLK_CFG_7 0x0080
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#define CLK_CFG_8 0x0090
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#define CLK_CFG_11 0x00c0
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#define CLK_CFG_12 0x00d0
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#define CLK_CFG_13 0x00e0
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#define CLK_CFG_15 0x0100
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#define CLK_AUDDIV_0 0x0320
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#define CLK_AUDDIV_2 0x0328
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#define CLK_AUDDIV_3 0x0334
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#define CLK_AUDDIV_4 0x0338
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#define CKSYS_AUD_TOP_CFG 0x032c
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#define CKSYS_AUD_TOP_MON 0x0330
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#define PERI_BUS_DCM_CTRL 0x0074
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#define MODULE_SW_CG_1_STA 0x0094
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#define MODULE_SW_CG_2_STA 0x00ac
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/* CLK_AUDDIV_0 */
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#define APLL12_DIV0_PDN_SFT 0
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#define APLL12_DIV0_PDN_MASK 0x1
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#define APLL12_DIV0_PDN_MASK_SFT (0x1 << 0)
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#define APLL12_DIV1_PDN_SFT 1
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#define APLL12_DIV1_PDN_MASK 0x1
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#define APLL12_DIV1_PDN_MASK_SFT (0x1 << 1)
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#define APLL12_DIV2_PDN_SFT 2
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#define APLL12_DIV2_PDN_MASK 0x1
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#define APLL12_DIV2_PDN_MASK_SFT (0x1 << 2)
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#define APLL12_DIV3_PDN_SFT 3
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#define APLL12_DIV3_PDN_MASK 0x1
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#define APLL12_DIV3_PDN_MASK_SFT (0x1 << 3)
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#define APLL12_DIV4_PDN_SFT 4
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#define APLL12_DIV4_PDN_MASK 0x1
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#define APLL12_DIV4_PDN_MASK_SFT (0x1 << 4)
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#define APLL12_DIVB_PDN_SFT 5
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#define APLL12_DIVB_PDN_MASK 0x1
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#define APLL12_DIVB_PDN_MASK_SFT (0x1 << 5)
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#define APLL12_DIV5_PDN_SFT 6
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#define APLL12_DIV5_PDN_MASK 0x1
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#define APLL12_DIV5_PDN_MASK_SFT (0x1 << 6)
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#define APLL_I2S0_MCK_SEL_SFT 16
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#define APLL_I2S0_MCK_SEL_MASK 0x1
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#define APLL_I2S0_MCK_SEL_MASK_SFT (0x1 << 16)
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#define APLL_I2S1_MCK_SEL_SFT 17
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#define APLL_I2S1_MCK_SEL_MASK 0x1
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#define APLL_I2S1_MCK_SEL_MASK_SFT (0x1 << 17)
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#define APLL_I2S2_MCK_SEL_SFT 18
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#define APLL_I2S2_MCK_SEL_MASK 0x1
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#define APLL_I2S2_MCK_SEL_MASK_SFT (0x1 << 18)
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#define APLL_I2S3_MCK_SEL_SFT 19
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#define APLL_I2S3_MCK_SEL_MASK 0x1
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#define APLL_I2S3_MCK_SEL_MASK_SFT (0x1 << 19)
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#define APLL_I2S4_MCK_SEL_SFT 20
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#define APLL_I2S4_MCK_SEL_MASK 0x1
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#define APLL_I2S4_MCK_SEL_MASK_SFT (0x1 << 20)
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#define APLL_I2S5_MCK_SEL_SFT 21
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#define APLL_I2S5_MCK_SEL_MASK 0x1
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#define APLL_I2S5_MCK_SEL_MASK_SFT (0x1 << 21)
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/* CLK_AUDDIV_2 */
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#define APLL12_CK_DIV0_SFT 0
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#define APLL12_CK_DIV0_MASK 0xff
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#define APLL12_CK_DIV0_MASK_SFT (0xff << 0)
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#define APLL12_CK_DIV1_SFT 8
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#define APLL12_CK_DIV1_MASK 0xff
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#define APLL12_CK_DIV1_MASK_SFT (0xff << 8)
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#define APLL12_CK_DIV2_SFT 16
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#define APLL12_CK_DIV2_MASK 0xff
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#define APLL12_CK_DIV2_MASK_SFT (0xff << 16)
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#define APLL12_CK_DIV3_SFT 24
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#define APLL12_CK_DIV3_MASK 0xff
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#define APLL12_CK_DIV3_MASK_SFT (0xff << 24)
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/* CLK_AUDDIV_3 */
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#define APLL12_CK_DIV4_SFT 0
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#define APLL12_CK_DIV4_MASK 0xff
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#define APLL12_CK_DIV4_MASK_SFT (0xff << 0)
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#define APLL12_CK_DIVB_SFT 8
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#define APLL12_CK_DIVB_MASK 0xff
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#define APLL12_CK_DIVB_MASK_SFT (0xff << 8)
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#define APLL12_CK_DIV5_SFT 16
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#define APLL12_CK_DIV5_MASK 0xff
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#define APLL12_CK_DIV5_MASK_SFT (0xff << 16)
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/* AUD_TOP_CFG */
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#define AUD_TOP_CFG_SFT 0
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#define AUD_TOP_CFG_MASK 0xffffffff
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#define AUD_TOP_CFG_MASK_SFT (0xffffffff << 0)
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/* AUD_TOP_MON */
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#define AUD_TOP_MON_SFT 0
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#define AUD_TOP_MON_MASK 0xffffffff
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#define AUD_TOP_MON_MASK_SFT (0xffffffff << 0)
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/* CLK_AUDDIV_3 */
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#define APLL12_CK_DIV5_MSB_SFT 0
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#define APLL12_CK_DIV5_MSB_MASK 0xf
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#define APLL12_CK_DIV5_MSB_MASK_SFT (0xf << 0)
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#define RESERVED0_SFT 4
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#define RESERVED0_MASK 0xfffffff
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#define RESERVED0_MASK_SFT (0xfffffff << 4)
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/* APLL */
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#define APLL1_W_NAME "APLL1"
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#define APLL2_W_NAME "APLL2"
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enum {
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MT6833_APLL1 = 0,
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MT6833_APLL2,
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};
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enum {
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CLK_AFE = 0,
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/*CLK_DAC,*/
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/*CLK_DAC_PREDIS,*/
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/*CLK_ADC,*/
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CLK_TML,
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CLK_APLL22M,
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CLK_APLL24M,
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CLK_APLL1_TUNER,
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CLK_APLL2_TUNER,
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CLK_NLE,
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CLK_SCP_SYS_AUD,
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CLK_INFRA_SYS_AUDIO,
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CLK_INFRA_AUDIO_26M,
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CLK_MUX_AUDIO,
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CLK_MUX_AUDIOINTBUS,
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CLK_TOP_MAINPLL_D4_D4,
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/* apll related mux */
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CLK_TOP_MUX_AUD_1,
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CLK_TOP_APLL1_CK,
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CLK_TOP_MUX_AUD_2,
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CLK_TOP_APLL2_CK,
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CLK_TOP_MUX_AUD_ENG1,
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CLK_TOP_APLL1_D8,
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CLK_TOP_MUX_AUD_ENG2,
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CLK_TOP_APLL2_D8,
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CLK_TOP_MUX_AUDIO_H,
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CLK_TOP_I2S0_M_SEL,
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CLK_TOP_I2S1_M_SEL,
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CLK_TOP_I2S2_M_SEL,
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CLK_TOP_I2S3_M_SEL,
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CLK_TOP_I2S4_M_SEL,
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CLK_TOP_I2S5_M_SEL,
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CLK_TOP_APLL12_DIV0,
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CLK_TOP_APLL12_DIV1,
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CLK_TOP_APLL12_DIV2,
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CLK_TOP_APLL12_DIV3,
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CLK_TOP_APLL12_DIV4,
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CLK_TOP_APLL12_DIVB,
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CLK_TOP_APLL12_DIV5,
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CLK_CLK26M,
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CLK_NUM
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};
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struct mtk_base_afe;
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int mt6833_init_clock(struct mtk_base_afe *afe);
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int mt6833_afe_enable_clock(struct mtk_base_afe *afe);
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void mt6833_afe_disable_clock(struct mtk_base_afe *afe);
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int mt6833_afe_dram_request(struct device *dev);
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int mt6833_afe_dram_release(struct device *dev);
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int mt6833_apll1_enable(struct mtk_base_afe *afe);
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void mt6833_apll1_disable(struct mtk_base_afe *afe);
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int mt6833_apll2_enable(struct mtk_base_afe *afe);
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void mt6833_apll2_disable(struct mtk_base_afe *afe);
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int mt6833_get_apll_rate(struct mtk_base_afe *afe, int apll);
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int mt6833_get_apll_by_rate(struct mtk_base_afe *afe, int rate);
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int mt6833_get_apll_by_name(struct mtk_base_afe *afe, const char *name);
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extern void aud_intbus_mux_sel(unsigned int aud_idx);
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/* these will be replaced by using CCF */
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int mt6833_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate);
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void mt6833_mck_disable(struct mtk_base_afe *afe, int mck_id);
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int mt6833_set_audio_int_bus_parent(struct mtk_base_afe *afe,
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int clk_id);
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#endif
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