142 lines
4 KiB
C
142 lines
4 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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//
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// Copyright (c) 2018 BayLibre, SAS.
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// Author: Jerome Brunet <jbrunet@baylibre.com>
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/* This driver implements the frontend playback DAI of AXG based SoCs */
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <sound/soc.h>
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#include <sound/soc-dai.h>
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#include "axg-fifo.h"
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#define CTRL0_FRDDR_PP_MODE BIT(30)
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static int axg_frddr_dai_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
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unsigned int fifo_depth, fifo_threshold;
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int ret;
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/* Enable pclk to access registers and clock the fifo ip */
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ret = clk_prepare_enable(fifo->pclk);
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if (ret)
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return ret;
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/* Apply single buffer mode to the interface */
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regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_FRDDR_PP_MODE, 0);
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/*
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* TODO: We could adapt the fifo depth and the fifo threshold
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* depending on the expected memory throughput and lantencies
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* For now, we'll just use the same values as the vendor kernel
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* Depth and threshold are zero based.
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*/
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fifo_depth = AXG_FIFO_MIN_CNT - 1;
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fifo_threshold = (AXG_FIFO_MIN_CNT / 2) - 1;
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regmap_update_bits(fifo->map, FIFO_CTRL1,
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CTRL1_FRDDR_DEPTH_MASK | CTRL1_THRESHOLD_MASK,
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CTRL1_FRDDR_DEPTH(fifo_depth) |
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CTRL1_THRESHOLD(fifo_threshold));
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return 0;
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}
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static void axg_frddr_dai_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
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clk_disable_unprepare(fifo->pclk);
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}
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static int axg_frddr_pcm_new(struct snd_soc_pcm_runtime *rtd,
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struct snd_soc_dai *dai)
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{
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return axg_fifo_pcm_new(rtd, SNDRV_PCM_STREAM_PLAYBACK);
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}
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static const struct snd_soc_dai_ops axg_frddr_ops = {
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.startup = axg_frddr_dai_startup,
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.shutdown = axg_frddr_dai_shutdown,
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};
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static struct snd_soc_dai_driver axg_frddr_dai_drv = {
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.name = "FRDDR",
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.playback = {
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.stream_name = "Playback",
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.channels_min = 1,
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.channels_max = AXG_FIFO_CH_MAX,
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.rates = AXG_FIFO_RATES,
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.formats = AXG_FIFO_FORMATS,
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},
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.ops = &axg_frddr_ops,
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.pcm_new = axg_frddr_pcm_new,
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};
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static const char * const axg_frddr_sel_texts[] = {
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"OUT 0", "OUT 1", "OUT 2", "OUT 3"
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};
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static SOC_ENUM_SINGLE_DECL(axg_frddr_sel_enum, FIFO_CTRL0, CTRL0_SEL_SHIFT,
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axg_frddr_sel_texts);
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static const struct snd_kcontrol_new axg_frddr_out_demux =
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SOC_DAPM_ENUM("Output Sink", axg_frddr_sel_enum);
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static const struct snd_soc_dapm_widget axg_frddr_dapm_widgets[] = {
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SND_SOC_DAPM_DEMUX("SINK SEL", SND_SOC_NOPM, 0, 0,
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&axg_frddr_out_demux),
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SND_SOC_DAPM_AIF_OUT("OUT 0", NULL, 0, SND_SOC_NOPM, 0, 0),
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SND_SOC_DAPM_AIF_OUT("OUT 1", NULL, 0, SND_SOC_NOPM, 0, 0),
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SND_SOC_DAPM_AIF_OUT("OUT 2", NULL, 0, SND_SOC_NOPM, 0, 0),
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SND_SOC_DAPM_AIF_OUT("OUT 3", NULL, 0, SND_SOC_NOPM, 0, 0),
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};
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static const struct snd_soc_dapm_route axg_frddr_dapm_routes[] = {
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{ "SINK SEL", NULL, "Playback" },
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{ "OUT 0", "OUT 0", "SINK SEL" },
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{ "OUT 1", "OUT 1", "SINK SEL" },
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{ "OUT 2", "OUT 2", "SINK SEL" },
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{ "OUT 3", "OUT 3", "SINK SEL" },
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};
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static const struct snd_soc_component_driver axg_frddr_component_drv = {
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.dapm_widgets = axg_frddr_dapm_widgets,
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.num_dapm_widgets = ARRAY_SIZE(axg_frddr_dapm_widgets),
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.dapm_routes = axg_frddr_dapm_routes,
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.num_dapm_routes = ARRAY_SIZE(axg_frddr_dapm_routes),
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.ops = &axg_fifo_pcm_ops
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};
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static const struct axg_fifo_match_data axg_frddr_match_data = {
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.component_drv = &axg_frddr_component_drv,
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.dai_drv = &axg_frddr_dai_drv
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};
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static const struct of_device_id axg_frddr_of_match[] = {
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{
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.compatible = "amlogic,axg-frddr",
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.data = &axg_frddr_match_data,
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}, {}
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};
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MODULE_DEVICE_TABLE(of, axg_frddr_of_match);
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static struct platform_driver axg_frddr_pdrv = {
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.probe = axg_fifo_probe,
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.driver = {
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.name = "axg-frddr",
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.of_match_table = axg_frddr_of_match,
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},
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};
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module_platform_driver(axg_frddr_pdrv);
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MODULE_DESCRIPTION("Amlogic AXG playback fifo driver");
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MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
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MODULE_LICENSE("GPL v2");
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