256 lines
8 KiB
Plaintext
256 lines
8 KiB
Plaintext
One-register-per-pin type device tree based pinctrl driver
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Required properties:
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- compatible : "pinctrl-single" or "pinconf-single".
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"pinctrl-single" means that pinconf isn't supported.
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"pinconf-single" means that generic pinconf is supported.
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- reg : offset and length of the register set for the mux registers
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- #pinctrl-cells : number of cells in addition to the index, set to 1
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for pinctrl-single,pins and 2 for pinctrl-single,bits
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- pinctrl-single,register-width : pinmux register access width in bits
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- pinctrl-single,function-mask : mask of allowed pinmux function bits
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in the pinmux register
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Optional properties:
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- pinctrl-single,function-off : function off mode for disabled state if
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available and same for all registers; if not specified, disabling of
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pin functions is ignored
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- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
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more than one pin, for which "pinctrl-single,function-mask" property specifies
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position mask of pin.
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- pinctrl-single,drive-strength : array of value that are used to configure
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drive strength in the pinmux register. They're value of drive strength
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current and drive strength mask.
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/* drive strength current, mask */
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pinctrl-single,power-source = <0x30 0xf0>;
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- pinctrl-single,bias-pullup : array of value that are used to configure the
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input bias pullup in the pinmux register.
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/* input, enabled pullup bits, disabled pullup bits, mask */
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pinctrl-single,bias-pullup = <0 1 0 1>;
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- pinctrl-single,bias-pulldown : array of value that are used to configure the
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input bias pulldown in the pinmux register.
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/* input, enabled pulldown bits, disabled pulldown bits, mask */
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pinctrl-single,bias-pulldown = <2 2 0 2>;
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* Two bits to control input bias pullup and pulldown: User should use
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pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means
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pullup, and the other one bit means pulldown.
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* Three bits to control input bias enable, pullup and pulldown. User should
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use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias
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enable bit should be included in pullup or pulldown bits.
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* Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as
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pinctrl-single,bias-disable. Because pinctrl single driver could implement
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it by calling pulldown, pullup disabled.
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- pinctrl-single,input-schmitt : array of value that are used to configure
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input schmitt in the pinmux register. In some silicons, there're two input
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schmitt value (rising-edge & falling-edge) in the pinmux register.
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/* input schmitt value, mask */
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pinctrl-single,input-schmitt = <0x30 0x70>;
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- pinctrl-single,input-schmitt-enable : array of value that are used to
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configure input schmitt enable or disable in the pinmux register.
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/* input, enable bits, disable bits, mask */
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pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;
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- pinctrl-single,low-power-mode : array of value that are used to configure
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low power mode of this pin. For some silicons, the low power mode will
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control the output of the pin when the pad including the pin enter low
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power mode.
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/* low power mode value, mask */
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pinctrl-single,low-power-mode = <0x288 0x388>;
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- pinctrl-single,gpio-range : list of value that are used to configure a GPIO
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range. They're value of subnode phandle, pin base in pinctrl device, pin
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number in this range, GPIO function value of this GPIO range.
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The number of parameters is depend on #pinctrl-single,gpio-range-cells
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property.
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/* pin base, nr pins & gpio function */
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pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>;
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- interrupt-controller : standard interrupt controller binding if using
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interrupts for wake-up events for example. In this case pinctrl-single
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is set up as a chained interrupt controller and the wake-up interrupts
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can be requested by the drivers using request_irq().
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- #interrupt-cells : standard interrupt binding if using interrupts
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This driver assumes that there is only one register for each pin (unless the
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pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
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specified in the pinctrl-bindings.txt document in this directory.
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The pin configuration nodes for pinctrl-single are specified as pinctrl
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register offset and value pairs using pinctrl-single,pins. Only the bits
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specified in pinctrl-single,function-mask are updated. For example, setting
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a pin for a device could be done with:
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pinctrl-single,pins = <0xdc 0x118>;
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Where 0xdc is the offset from the pinctrl register base address for the
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device pinctrl register, and 0x118 contains the desired value of the
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pinctrl register. See the device example and static board pins example
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below for more information.
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In case when one register changes more than one pin's mux the
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pinctrl-single,bits need to be used which takes three parameters:
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pinctrl-single,bits = <0xdc 0x18 0xff>;
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Where 0xdc is the offset from the pinctrl register base address for the
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device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
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be used when applying this change to the register.
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Optional sub-node: In case some pins could be configured as GPIO in the pinmux
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register, those pins could be defined as a GPIO range. This sub-node is required
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by pinctrl-single,gpio-range property.
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Required properties in sub-node:
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- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in
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pinctrl-single,gpio-range property.
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range: gpio-range {
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#pinctrl-single,gpio-range-cells = <3>;
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};
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Example:
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/* SoC common file */
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/* first controller instance for pins in core domain */
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pmx_core: pinmux@4a100040 {
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compatible = "pinctrl-single";
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reg = <0x4a100040 0x0196>;
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#address-cells = <1>;
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#size-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0xffff>;
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};
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/* second controller instance for pins in wkup domain */
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pmx_wkup: pinmux@4a31e040 {
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compatible = "pinctrl-single";
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reg = <0x4a31e040 0x0038>;
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#address-cells = <1>;
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#size-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0xffff>;
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};
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control_devconf0: pinmux@48002274 {
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compatible = "pinctrl-single";
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reg = <0x48002274 4>; /* Single register */
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-single,bit-per-mux;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x5F>;
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};
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/* third controller instance for pins in gpio domain */
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pmx_gpio: pinmux@d401e000 {
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compatible = "pinconf-single";
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reg = <0xd401e000 0x0330>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <7>;
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/* sparse GPIO range could be supported */
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pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
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&range 12 1 0 &range 13 29 1
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&range 43 1 0 &range 44 49 1
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&range 94 1 1 &range 96 2 1>;
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range: gpio-range {
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#pinctrl-single,gpio-range-cells = <3>;
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};
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};
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/* board specific .dts file */
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&pmx_core {
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/*
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* map all board specific static pins enabled by the pinctrl driver
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* itself during the boot (or just set them up in the bootloader)
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*/
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pinctrl-names = "default";
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pinctrl-0 = <&board_pins>;
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board_pins: pinmux_board_pins {
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pinctrl-single,pins = <
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0x6c 0xf
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0x6e 0xf
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0x70 0xf
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0x72 0xf
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>;
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};
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uart0_pins: pinmux_uart0_pins {
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pinctrl-single,pins = <
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0x208 0 /* UART0_RXD (IOCFG138) */
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0x20c 0 /* UART0_TXD (IOCFG139) */
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>;
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pinctrl-single,bias-pulldown = <0 2 2>;
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pinctrl-single,bias-pullup = <0 1 1>;
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};
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/* map uart2 pins */
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uart2_pins: pinmux_uart2_pins {
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pinctrl-single,pins = <
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0xd8 0x118
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0xda 0
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0xdc 0x118
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0xde 0
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>;
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};
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};
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&control_devconf0 {
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mcbsp1_pins: pinmux_mcbsp1_pins {
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pinctrl-single,bits = <
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0x00 0x18 0x18 /* FSR/CLKR signal from FSX/CLKX pin */
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>;
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};
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mcbsp2_clks_pins: pinmux_mcbsp2_clks_pins {
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pinctrl-single,bits = <
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0x00 0x40 0x40 /* McBSP2 CLKS from McBSP_CLKS pin */
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>;
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};
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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};
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