48 lines
1.5 KiB
Plaintext
48 lines
1.5 KiB
Plaintext
* Pin configuration for TI IODELAY controller
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TI dra7 based SoCs such as am57xx have a controller for setting the IO delay
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for each pin. For most part the IO delay values are programmed by the bootloader,
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but some pins need to be configured dynamically by the kernel such as the
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MMC pins.
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Required Properties:
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- compatible: Must be "ti,dra7-iodelay"
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- reg: Base address and length of the memory resource used
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- #address-cells: Number of address cells
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- #size-cells: Size of cells
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- #pinctrl-cells: Number of pinctrl cells, must be 2. See also
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Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
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Example
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-------
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In the SoC specific dtsi file:
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dra7_iodelay_core: padconf@4844a000 {
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compatible = "ti,dra7-iodelay";
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reg = <0x4844a000 0x0d1c>;
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#address-cells = <1>;
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#size-cells = <0>;
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#pinctrl-cells = <2>;
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};
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In board-specific file:
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&dra7_iodelay_core {
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mmc2_iodelay_3v3_conf: mmc2_iodelay_3v3_conf {
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pinctrl-pin-array = <
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0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */
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0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */
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0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */
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0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */
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0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */
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0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */
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0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
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0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */
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0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */
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0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */
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>;
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};
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};
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