220 lines
5 KiB
C
220 lines
5 KiB
C
/*
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* Broadcom BCM63138 PMB initialization for secondary CPU(s)
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*
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* Copyright (C) 2015 Broadcom Corporation
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* Author: Florian Fainelli <f.fainelli@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <linux/reset/bcm63xx_pmb.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "bcm63xx_smp.h"
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/* ARM Control register definitions */
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#define CORE_PWR_CTRL_SHIFT 0
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#define CORE_PWR_CTRL_MASK 0x3
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#define PLL_PWR_ON BIT(8)
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#define PLL_LDO_PWR_ON BIT(9)
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#define PLL_CLAMP_ON BIT(10)
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#define CPU_RESET_N(x) BIT(13 + (x))
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#define NEON_RESET_N BIT(15)
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#define PWR_CTRL_STATUS_SHIFT 28
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#define PWR_CTRL_STATUS_MASK 0x3
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#define PWR_DOWN_SHIFT 30
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#define PWR_DOWN_MASK 0x3
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/* CPU Power control register definitions */
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#define MEM_PWR_OK BIT(0)
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#define MEM_PWR_ON BIT(1)
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#define MEM_CLAMP_ON BIT(2)
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#define MEM_PWR_OK_STATUS BIT(4)
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#define MEM_PWR_ON_STATUS BIT(5)
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#define MEM_PDA_SHIFT 8
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#define MEM_PDA_MASK 0xf
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#define MEM_PDA_CPU_MASK 0x1
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#define MEM_PDA_NEON_MASK 0xf
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#define CLAMP_ON BIT(15)
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#define PWR_OK_SHIFT 16
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#define PWR_OK_MASK 0xf
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#define PWR_ON_SHIFT 20
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#define PWR_CPU_MASK 0x03
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#define PWR_NEON_MASK 0x01
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#define PWR_ON_MASK 0xf
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#define PWR_OK_STATUS_SHIFT 24
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#define PWR_OK_STATUS_MASK 0xf
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#define PWR_ON_STATUS_SHIFT 28
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#define PWR_ON_STATUS_MASK 0xf
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#define ARM_CONTROL 0x30
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#define ARM_PWR_CONTROL_BASE 0x34
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#define ARM_PWR_CONTROL(x) (ARM_PWR_CONTROL_BASE + (x) * 0x4)
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#define ARM_NEON_L2 0x3c
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/* Perform a value write, then spin until the value shifted by
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* shift is seen, masked with mask and is different from cond.
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*/
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static int bpcm_wr_rd_mask(void __iomem *master,
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unsigned int addr, u32 off, u32 *val,
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u32 shift, u32 mask, u32 cond)
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{
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int ret;
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ret = bpcm_wr(master, addr, off, *val);
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if (ret)
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return ret;
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do {
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ret = bpcm_rd(master, addr, off, val);
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if (ret)
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return ret;
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cpu_relax();
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} while (((*val >> shift) & mask) != cond);
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return ret;
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}
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/* Global lock to serialize accesses to the PMB registers while we
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* are bringing up the secondary CPU
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*/
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static DEFINE_SPINLOCK(pmb_lock);
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static int bcm63xx_pmb_get_resources(struct device_node *dn,
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void __iomem **base,
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unsigned int *cpu,
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unsigned int *addr)
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{
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struct of_phandle_args args;
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int ret;
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ret = of_property_read_u32(dn, "reg", cpu);
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if (ret) {
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pr_err("CPU is missing a reg node\n");
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return ret;
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}
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ret = of_parse_phandle_with_args(dn, "resets", "#reset-cells",
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0, &args);
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if (ret) {
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pr_err("CPU is missing a resets phandle\n");
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return ret;
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}
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if (args.args_count != 2) {
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pr_err("reset-controller does not conform to reset-cells\n");
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return -EINVAL;
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}
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*base = of_iomap(args.np, 0);
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if (!*base) {
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pr_err("failed remapping PMB register\n");
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return -ENOMEM;
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}
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/* We do not need the number of zones */
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*addr = args.args[0];
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return 0;
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}
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int bcm63xx_pmb_power_on_cpu(struct device_node *dn)
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{
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void __iomem *base;
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unsigned int cpu, addr;
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unsigned long flags;
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u32 val, ctrl;
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int ret;
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ret = bcm63xx_pmb_get_resources(dn, &base, &cpu, &addr);
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if (ret)
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return ret;
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/* We would not know how to enable a third and greater CPU */
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WARN_ON(cpu > 1);
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spin_lock_irqsave(&pmb_lock, flags);
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/* Check if the CPU is already on and save the ARM_CONTROL register
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* value since we will use it later for CPU de-assert once done with
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* the CPU-specific power sequence
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*/
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ret = bpcm_rd(base, addr, ARM_CONTROL, &ctrl);
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if (ret)
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goto out;
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if (ctrl & CPU_RESET_N(cpu)) {
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pr_info("PMB: CPU%d is already powered on\n", cpu);
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ret = 0;
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goto out;
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}
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/* Power on PLL */
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ret = bpcm_rd(base, addr, ARM_PWR_CONTROL(cpu), &val);
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if (ret)
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goto out;
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val |= (PWR_CPU_MASK << PWR_ON_SHIFT);
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ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val,
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PWR_ON_STATUS_SHIFT, PWR_CPU_MASK, PWR_CPU_MASK);
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if (ret)
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goto out;
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val |= (PWR_CPU_MASK << PWR_OK_SHIFT);
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ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val,
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PWR_OK_STATUS_SHIFT, PWR_CPU_MASK, PWR_CPU_MASK);
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if (ret)
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goto out;
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val &= ~CLAMP_ON;
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ret = bpcm_wr(base, addr, ARM_PWR_CONTROL(cpu), val);
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if (ret)
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goto out;
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/* Power on CPU<N> RAM */
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val &= ~(MEM_PDA_MASK << MEM_PDA_SHIFT);
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ret = bpcm_wr(base, addr, ARM_PWR_CONTROL(cpu), val);
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if (ret)
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goto out;
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val |= MEM_PWR_ON;
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ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val,
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0, MEM_PWR_ON_STATUS, MEM_PWR_ON_STATUS);
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if (ret)
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goto out;
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val |= MEM_PWR_OK;
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ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val,
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0, MEM_PWR_OK_STATUS, MEM_PWR_OK_STATUS);
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if (ret)
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goto out;
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val &= ~MEM_CLAMP_ON;
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ret = bpcm_wr(base, addr, ARM_PWR_CONTROL(cpu), val);
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if (ret)
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goto out;
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/* De-assert CPU reset */
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ctrl |= CPU_RESET_N(cpu);
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ret = bpcm_wr(base, addr, ARM_CONTROL, ctrl);
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out:
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spin_unlock_irqrestore(&pmb_lock, flags);
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iounmap(base);
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return ret;
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}
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