298 lines
7.3 KiB
Plaintext
298 lines
7.3 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
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/*
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* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/sun50i-h6-ccu.h>
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#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
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#include <dt-bindings/reset/sun50i-h6-ccu.h>
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#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <1>;
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enable-method = "psci";
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <2>;
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enable-method = "psci";
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <3>;
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enable-method = "psci";
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};
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};
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iosc: internal-osc-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <16000000>;
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clock-accuracy = <300000000>;
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clock-output-names = "iosc";
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};
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osc24M: osc24M_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc32k: osc32k_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ccu: clock@3001000 {
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compatible = "allwinner,sun50i-h6-ccu";
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reg = <0x03001000 0x1000>;
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clocks = <&osc24M>, <&osc32k>, <&iosc>;
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clock-names = "hosc", "losc", "iosc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pio: pinctrl@300b000 {
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compatible = "allwinner,sun50i-h6-pinctrl";
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reg = <0x0300b000 0x400>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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#gpio-cells = <3>;
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interrupt-controller;
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#interrupt-cells = <3>;
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mmc0_pins: mmc0-pins {
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pins = "PF0", "PF1", "PF2", "PF3",
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"PF4", "PF5";
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function = "mmc0";
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drive-strength = <30>;
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bias-pull-up;
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};
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mmc2_pins: mmc2-pins {
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pins = "PC1", "PC4", "PC5", "PC6",
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"PC7", "PC8", "PC9", "PC10",
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"PC11", "PC12", "PC13", "PC14";
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function = "mmc2";
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drive-strength = <30>;
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bias-pull-up;
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};
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uart0_ph_pins: uart0-ph {
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pins = "PH0", "PH1";
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function = "uart0";
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};
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};
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gic: interrupt-controller@3021000 {
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compatible = "arm,gic-400";
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reg = <0x03021000 0x1000>,
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<0x03022000 0x2000>,
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<0x03024000 0x2000>,
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<0x03026000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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mmc0: mmc@4020000 {
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compatible = "allwinner,sun50i-h6-mmc",
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"allwinner,sun50i-a64-mmc";
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reg = <0x04020000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC0>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@4021000 {
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compatible = "allwinner,sun50i-h6-mmc",
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"allwinner,sun50i-a64-mmc";
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reg = <0x04021000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC1>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc2: mmc@4022000 {
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compatible = "allwinner,sun50i-h6-emmc",
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"allwinner,sun50i-a64-emmc";
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reg = <0x04022000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC2>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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uart0: serial@5000000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x05000000 0x400>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART0>;
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resets = <&ccu RST_BUS_UART0>;
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status = "disabled";
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};
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uart1: serial@5000400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x05000400 0x400>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART1>;
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resets = <&ccu RST_BUS_UART1>;
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status = "disabled";
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};
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uart2: serial@5000800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x05000800 0x400>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART2>;
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resets = <&ccu RST_BUS_UART2>;
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status = "disabled";
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};
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uart3: serial@5000c00 {
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compatible = "snps,dw-apb-uart";
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reg = <0x05000c00 0x400>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART3>;
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resets = <&ccu RST_BUS_UART3>;
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status = "disabled";
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};
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r_ccu: clock@7010000 {
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compatible = "allwinner,sun50i-h6-r-ccu";
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reg = <0x07010000 0x400>;
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clocks = <&osc24M>, <&osc32k>, <&iosc>,
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<&ccu CLK_PLL_PERIPH0>;
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clock-names = "hosc", "losc", "iosc", "pll-periph";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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r_intc: interrupt-controller@7021000 {
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compatible = "allwinner,sun50i-h6-r-intc",
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"allwinner,sun6i-a31-r-intc";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x07021000 0x400>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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};
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r_pio: pinctrl@7022000 {
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compatible = "allwinner,sun50i-h6-r-pinctrl";
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reg = <0x07022000 0x400>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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#gpio-cells = <3>;
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interrupt-controller;
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#interrupt-cells = <3>;
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r_i2c_pins: r-i2c {
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pins = "PL0", "PL1";
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function = "s_i2c";
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};
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};
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r_i2c: i2c@7081400 {
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x07081400 0x400>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&r_ccu CLK_R_APB2_I2C>;
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resets = <&r_ccu RST_R_APB2_I2C>;
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pinctrl-names = "default";
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pinctrl-0 = <&r_i2c_pins>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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